Main memory

Computer hardware storage unit

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This entry is made by Compilation and application of scientific encyclopedia entries of "Science Popularization China" to examine.

main storage (Main memory) Main storage 。 yes computer hardware It is an important part of instructions And data, and can be controlled by a central processor (CPU) Direct random access 。 modern computer In order to improve performance and give consideration to reasonable cost Multilevel storage system 。 That is storage capacity Small, Access speed High Cache memory Main memory with moderate storage capacity and access speed is essential. main storage The device stores information by address, and the access speed is generally independent of the address. 32-bit (bit) address can express 4GB Memory address 。 This is enough for most applications, but it is not enough for some applications with extremely large amount of computation and large databases, thus requiring a 64 bit structure.

Chinese name: Main memory
Foreign name: Mainmemory
Alias: Main storage

importance: A component of computer hardware
Role: Store instructions and data
At present: 64 bit

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Development Introduction

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Main memory generally adopts Semiconductor memory , and Auxiliary memory Compared with small capacity, fast reading and writing speed, high price, etc. The main memory in a computer is mainly composed of memory body Control line , address register, data register and address decoding circuit.

Since the 1970s storage The device has been gradually adopted large-scale integrated circuit Composition. The most common and economical dynamic Random access memory Chip (DRAM). In 1995, the integration degree was 64Mb ( storage 4 million Chinese characters) and 16Mb DRAM chips have become mainstream products in the market. DRAM chip Access speed Moderate, generally 50-70ns. There are some improved DRAMs, such as EDO DRAM (i.e. expansion data output DRAM), its performance can be improved by more than 10% compared with ordinary DRAM, such as SDRAM (i.e. synchronous DRAM), its performance can be improved by about 10% compared with EDO DRAM. In 1998, the successor product of SDRAM was SDRAM II (or DDR, i.e. double Data rate ）A variety of has been launched. In the pursuit of speed and reliability, the more expensive SRAM Chip（ SRAM ）Its access speed can reach 1~15ns. Whether the main memory is composed of DRAM or SRAM chips storage Information will be "lost", so computer The designer should consider that when this happens, try to maintain power supply for several milliseconds to save important information in main memory, so that the computer can Return to normal function. In view of the above situation, in some applications storage Important and relatively fixed procedures and data adopt "non-volatile" storage Device chip (such as EPROM, flash Memory chip Etc.) composition; For completely fixed programs, the data area even adopts read-only memory (ROM) chip composition; These parts of main memory are not afraid of temporary Power supply interruption , can also prevent virus intrusion.

Technical indicators

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Indicator Meaning Performance Unit

KINGXCON DDR2-533

storage capacity That can be accommodated in one memory Storage unit total storage space Size, words, bytes

Access time Start to finish once storage The speed of main memory of the time experienced by the device operation ns

Storage cycle The speed of main memory of the minimum time interval required for two consecutive operations ns

Memory bandwidth Memory access per unit time information content , it is a measure Data transmission rate The importance of Technical indicators , the unit is b/s (bit/second) or B/S (byte/second).

Store a machine word Storage unit , commonly referred to as word storage unit, corresponding Unit address call Word address 。 The unit storing one byte is called byte Storage unit , the corresponding address is called Byte address 。 If computer Zhongke Addressing The smallest unit of is word Storage unit , the computer A computer called a word address. If the computer can Addressing Minimum order of

Gold finger in memory of electrogilding process

Bit is byte , the computer is called a byte addressed computer. A machine word can contain several bytes, so a Storage unit It can also contain several byte addresses that can be individually addressed. For example, PDP-11 series computer , a 16 bit Binary word Storage unit It can store two bytes, which can be addressed by word address or byte address. When addressing with byte address, 16 bit Storage unit Two byte address.

capacity

In a storage Contained in Storage unit The total is often referred to as the storage capacity of the memory. storage capacity It is expressed in words or bytes (B), such as 64K words, 512KB, 10 MB 。 External storage In order to represent larger storage capacity MB， GB ， TB Etc. Where 1KB=2 ^ 10B, 1MB=2 ^ 20B, 1GB=2 ^ 30B, 1TB=2 ^ 40B. B means byte , one byte is defined as 8 Binary Bit, so computer One word Word length Usually a multiple of 8. storage capacity This concept reflects storage space Size of.

time

also called storage Device access time or read/write time refers to the time from starting a memory operation to completing the operation. Specifically, from one read operation command When the operation is completed, read the data in Data buffer register The time elapsed until is Memory access time 。

cycle

It refers to two independent starts storage The minimum time interval required for a device operation (such as two consecutive read operations). Generally, the storage cycle is slightly longer than the storage time, which Time unit Is ns

Product classification

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RAM It is the main part of the memory. Its contents can be read or written at any time according to the address as required. It is stored in the state of some electric trigger. After power failure, the information cannot be saved. It is used to temporarily store data. It can also be divided into DRAM and SRAM Two. RAM generally uses dynamic semiconductor Memory device （DRAM）。 Because the CPU works Speed ratio The read and write speed of RAM is fast, so the CPU needs to spend time waiting when reading and writing RAM, which will reduce the CPU's working speed. In order to improve the speed of CPU reading and writing programs and data, RAM and CPU are added Cache (Cache) part. The contents of the Cache are copies of the contents of some storage units in random access memory (RAM).

ROM yes read-only memory , the contents of which are delivered by the factory Mask It can only be read, but cannot be rewritten. The information has been solidified in the memory, which is generally used to store system program BIOS and Microprogram control 。

PROM It is a programmable ROM and can only be written once (the same as ROM), but it can be used by the user after leaving the factory Electronic equipment Write.

EPROM Yes Erase PROM can be read or written. But you must use the Ultraviolet radiation , to erase all information, and then use EPROM The programmer Write. You can write multiple times.

EEPROM It is electrically erasable PROM. Similar to EPROM, it can be read or written. Before writing, it does not need to erase the previous contents, and it can directly modify the addressed bytes or blocks.

Flash memory (Flash Memory), whose characteristics are between EPROM and EEPROM. Flash memory can also be used electrical signal Fast deletion operation, much faster than EEPROM. However, byte level deletion is not allowed Integration Higher than EEPROM.^[1]

Connection control

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Capacity expansion

Model

because Memory chip Of capacity Limited, main storage It is usually composed of a certain number of chips Bit expansion : Bit expansion refers to expansion (increase) only in the number of bits Word length ）The number of words in the chip and the number of words in the memory. Bit expansion Of Connection mode Yes Memory chip Of Address line 、 Segment selection It is connected in parallel with the read/write line, and the data line Listed separately Word expansion : Word expansion refers to the expansion of the number of words without changing the number of digits. Word expansion Put the Address line 、 data line , reading and writing Control line In parallel, while Chip Select To distinguish the simultaneous expansion of each chip word and bit: capacity For larger containers, it is often necessary to Word number direction and Bit direction At the same time, expand.

Chip selection

Structural map

CPU To achieve Storage unit You must first select Memory chip , that is, film selection; Then click the Address code Selecting the corresponding storage unit for data access is called word selection. The on-chip word selection is N low bits sent by the CPU Address line Completed, the address line is directly connected to all Memory chip The address input terminal of the memory chip Chip Select It is mostly generated after decoding the high bit address.

Line selection method ：

Line selection is to use division On-chip addressing Outer high order Address line Directly connected to each Memory chip Of Film selection When the information of an address line is 0, select the corresponding memory chip. these ones here Film selection Address line Only one bit can be valid for each addressing, and multiple bits cannot be valid at the same time, so that only one chip can be selected at a time. The line selection method cannot make full use of the systematic storage Instrument space address space It is divided into mutually isolated areas, which brings some difficulties to programming.

whole decoding method ：

whole decoding Method: remove the inner part of the tablet addressing All high bits except Address line All as addresses decoder The output of the decoder is used as the input of each chip Chip Select , connect them to Memory chip To realize the selection of memory chips. whole decoding The advantage of the method is that the address range of each chip is unique, continuous, and easy to expand, without overlapping addresses storage However, the full decoding method requires a higher decoding circuit.

part decoding Method: The so-called partial decoding method uses a part of the high bit address other than the on-chip addressing to decode and generate Chip Select , partial decoding will produce address overlap.

Connection method

Main storage Between and CPU Hardwired : Main memory and CPU Hard copulation There are three groups of connections: Address bus （AB）、 data bus （ DB ）And Control bus （CB）。 Think of main memory as a black box, Memory address register (MAR) and storage Data register （ MDR ）It is the interface between main memory and CPU. MAR can receive data from Program counter (PC) Instruction address Or from Arithmetic unit Of Operands To determine which unit to access. The MDR is a buffer unit that writes data to or reads data from main memory. MAR and MDR belong to main memory in terms of function, but they are usually placed in the CPU.

Mimic diagram

Basic operation of CPU on main memory: When the CPU reads and writes to main memory, the CPU first gives the information on the address bus Address signal , and then issue the corresponding read/write command And exchange information on the data bus. The basic operations of reading and writing are as follows:

Read: Read operation It refers to the address sent from the CPU Storage unit Get the information from the and send it to the CPU. The operation process is as follows:

Address -->MAR -- ABCPU sends address signal to address bus

Send read command

WaitForMFC Wait storage Device work completion signal

M (MAR) -->DB -->MDR reads information to CPU via data bus

Write: Write refers to storing the information to be written into the CPU specified storage In the cell, the operation process is:

Address -->MAR -->ABCPU sends address signal to address bus

Data -->MDR -->The DBCPU sends the data to be written to the data bus

Send write command

WaitForMFC waits for the memory work completion signal

Speed matching between CPU and main memory: synchronization storage Device read and asynchronous memory read.

Asynchronous memory read : There is no unified clock between CPU and main memory, and the main memory work completion signal (MFC) informs the CPU that the main memory work has been completed.

Synchronous memory reading : The CPU and main memory use a unified clock to work synchronously. Because the main memory speed is slow, the CPU must slow down when cooperating with it. In this kind of memory, the main memory work completion signal is not required.

applied technology

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Fast read and write

Fast page working technology (Fast read/write technology of dynamic memory): When reading and writing data in the same line of dynamic memory Line Address The lock remains unchanged after the first read and write. When reading and writing data in multiple columns of the row later, only the column address can be locked, which saves the time for locking the row address and speeds up the main storage The read/write speed of the device.

EDO (ExtendedDataOut) technology : In terms of fast page work technology data output Partial data latching circuit, extending the validity of output data Holding time Thus, if the address signal is changed, the correct read data can still be obtained, which can further shorten the address input time and speed up the read/write speed of the main memory.

Parallel read and write

It means that storage The technology that can read multiple main memory words in one working cycle (or longer) of the processor.

Scheme 1: Integrated multi word structure, that is, add the Data bits , make it simultaneously storage Several main memory words are read at the same time for each read operation.

Scheme 2: Multi body crossing Addressing Technology storage The device is divided into several independent read-write Word length It is the main body of a main memory word memory bank Read and write; It can also make several memory bodies work together to provide a higher read/write speed than a single memory body.

There are two ways to read and write:

1 in the same Read write cycle Start all main memory reads or writes at the same time.

Main memory

2 Let the main memory read or write sequentially, that is, each read out in turn Storage word , which can be transmitted in turn through the data bus, without having to set special Data buffer register ; Secondly, we adopt Cross addressing In this way, several storage words with consecutive addresses are allocated to different storage bodies in turn. Because of the local characteristics of program operation, the probability of reading and writing adjacent main storage words with addresses in a short time is greater.

data transfer

so-called Group Data transmission means that the address bus can continuously transmit multiple data on the data bus after transmitting the address once. It used to use two Clock cycle : First send the address, and then send the data, that is, to transfer N data, 2N bus clock cycles are required, and the group data transmission mode only uses N+1 bus clock cycles.

Implement Grouping data transfer Mode, not only the CPU should support this operation mode, but also the main memory can provide a high enough data read/write speed, which is often through the multi-body structure of main memory Dynamic memory EDO support and other measures.

Static and dynamic

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static state

teaching computer Of Memory Accumulator Composition and design

(1) Static memory Storage principle and internal structure of the chip (P207)

(2) Teaching computer within storage Composition and design of the device

Address bus: AB15 ～ AB0, unified by Address register AR drive. The address register AR only receives the information output by ALU.

Control bus: the signal of control bus is controlled by decoder 74LS139 Give, the function is to indicate Bus cycle Type of:

（1） Memory Write cycle use MMW Signal marker

Related schematic diagram (2 sheets)

（2） Memory read cycle Mark with MMR signal

（3） peripheral (Interface) Write cycle is marked with IOW signal

（4） peripheral (Interface) Read cycle marked with IOR signal

(5) MMREQ signal mark for working in memory

(6) IOREQ signal mark for peripherals in operation

(7) Write control memory cycle is marked with SWA signal

Data bus: divided into internal data bus IB And External data bus DB consists of two parts. Main completion computer various Features Between data transfer 。 Design bus core technology Is to ensure that only one group can be Data transmission To the bus, one or more components are allowed to receive the information on the bus at the same time. The circuit used is usually a tristate gate circuit.

System clock Timely sequence: Teaching machine Crystal oscillator 1.8432MHz, 614.4KHz clock is used as the system after 3 frequency division Master clock , make CPU, memory IO Synchronous operation 。 Some internal CPU register At the end of the clock Rising edge Complete receiving data, and General register Yes Low level Received. During memory or I/O read/write operations, each bus cycle consists of two clocks. The first clock, called address time, is used to transmit addresses; The second clock, called data time, is used to read and write data

static state storage Word bit expansion of the processor:

Inside the teaching computer storage The device is implemented by static memory chip 2K Verbal ROM Zone and 2K word RAM District composition. Memory Word length 16 bits, addressing by word. ROM consists of 74LS2716 Read only memory ROM (2048 per piece Storage unit 8 bits per unit Binary Bit) Two pieces complete Word length Extension of. Address allocation: 0~2047RAM from 74LS6116 Random access memory RAM (2048 per chip Storage unit 8 bits per unit Binary Bit) Two pieces complete Word length Extension of. Address distribution: 2048~4095.

Static memory address allocation:

2048 for access Storage unit , use an 11 bit address to send the lower 11 bit address of the address bus to the address of each memory chip Pin ; The high bit of the address bus decoding , the decoding signal is sent to the/CS pin of each memory chip, and the byte Read and write.

dynamic

Dynamic memory Regular refresh of: When no read and write operations are performed, DRAM Each cell of the memory is in the power off state. Due to the existence of leakage, the charge stored on the capacitor CS will slowly leak out. Therefore, it must be supplemented regularly, called refresh operation.

(1) Dynamic memory Composition of: a single MOS tube stores one bit Binary Information. information storage In MOS tube Source pole Of Parasitic capacitance CS.

When writing data: Word line by High level , T conduction.

When writing "1", Bitline ( data line ）Is low level, VDD ( Power Supply ）Will charge the capacitor

When writing "0, bit line（ data line ）High level, if capacitance storage If the charge is applied, the capacitor will be discharged, indicating that "0" is stored.

When reading data: first change the bit line (data line) to High level , when the word line high level comes, T is on, if the capacitance is storage If there is a charge ("1"), the capacitance will be discharged, which will make the data line potential change from high to low; If the capacitor has no stored charge (is "0"), the data line potential will not change. testing data line The change of up potential can distinguish whether the data read is 1 or 0.

be careful

① Reading operation makes the capacitor original storage The charge is lost, and therefore the readout is destructive. In order to keep the original memory content, a write operation must be followed immediately after the read operation, called Precharge Delay.

② To Dynamic memory Of Storage unit Provide the address, which is to send the address first and then the address. The reason is right Dynamic memory It must be refreshed regularly (such as 2ms). The refresh is not performed by pressing Word processing , but refresh one row at a time, that is, connect all Storage unit The primary energy is supplemented by a capacitor of.

③ On Dynamic memory The readout signal on the bit line of is very small and must be connected for readout amplifier , usually used trigger line realization.

④ storage Internal Line Address And columns Address latch Accept the address of the line and column in order.

⑤ RAS, CAS, WE, Din, Dout timing relationship

Main memory optimization

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There is no lack of improvement data in the market storage New technologies of efficiency, however, most of these new technologies focus on backup and archiving rather than primary storage. However, when the enterprise starts to storage When reducing data, for them, understand Primary storage optimization Required necessary condition Very important.

main storage , often referred to as Level 1 storage, is characterized by storing active data that is often accessed and requires high performance and low time delay and High availability Data of. main storage Generally used to support Critical tasks Applications, such as databases Electronics Mail and transaction processing. Most key applications have random data access modes and different access requirements, but they all generate a large amount of data used by institutions to operate their businesses. Therefore, the organization makes many copies of the data, copies the data for distributed use, inventories the data, and then saves the backup and archive data for security.

Most data originates from master data 。 As data lives longer, they are usually migrated to Level 2 and Level 3 storage preservation. Therefore, if the organization can reduce the master data storage Space occupied , will be able to use these savings in the data life cycle capacity And fees. In other words, fewer masters storage Taking up space means less Data replication , inventory, archiving, and backups 。

Try to reduce the main storage Space occupied Storage management Personnel can consider two ways to reduce data: Real time compression And data de duplication.

Until recently, due to performance problems, data compression Has not been in the Lord storage It is widely used in application. However, Storwize and other manufacturers provide real-time random access The compression/decompression technology compresses the data space by 15:1 Solution 。 Higher compression ratio And real-time performance make compression solutions primary storage Possible options for data reduction.

The data de duplication technology widely used in backup applications is also being applied to the primary storage 。 So far, data de duplication faces a major challenge, that is, data de duplication is Offline processing 。 This is because the redundant data block Requires a lot of time and storage processor Do a lot of work, so very active data may be affected. At present, the main manufacturers of data de duplication technology include NetApp , Data Domain and Ocarina Networks 。

Main memory deployment

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Zero performance impact

With Backup or Archive storage Different, active data set Can be saved with some form of data reduction technology storage capacity More critical. Therefore, the selected data reduction technology must not affect performance. It must be effective and simple; It must be equivalent to "toggle a switch , consume less storage ”。

active storage The reduction solution only de duplicates the active storage when the data to be de duplicated reaches the inactive state. In other words, this means that only the Storage pool The files in the near active storage level are de duplicated.

The de duplication technology is recommended to work only for light I/O load Go back and avoid Performance bottlenecks 。 Therefore, the key components of IT infrastructure storage Not optimized. The database tops the list of key components. Because they are Level 1 storage And extremely active components and are almost always excluded from Light work In addition to loads, de reprocessing never analyzes them. Therefore, they are in the main storage The space occupied by is not optimized.

On the other hand, the real-time compression system compresses all data flowing through the compression system in real time. This leads to an unexpected benefit beyond saving storage capacity: improved storage performance. When all Data When compressed, the amount of data submitted by each I/O request effectively increases, the hard disk space increases, and each write and read operation becomes more efficient.

The actual result is the occupied hard disk capacity Decrease, overall storage Significantly improved performance.

main storage The second advantage of de duplication is that all data is reduced, which realizes the capacity Save. although Oracle The real-time data compression of the environment may cause some performance problems, but the tests so far show that the performance has improved.

Another question is yes storage The performance impact of the controller itself. People demand today's storage In addition to serving hard disks, the controller also needs to do many things, including managing different protocols, performing replication and managing snapshots. Adding another function to these functions may exceed the capacity of the controller -- even if it can handle the additional workload, it still adds one Storage management Personnel must be aware of processes that may become potential I/O bottlenecks. Send the compression work to the outside special equipment It eliminates a variable from the performance problem and does not give storage The controller has a slight impact.

High availability

Many concerns Level II storage 's data reduction solution is not highly available. This is because the backup or archive data they must restore immediately is not like the first level storage That's the key. But even at level two storage This concept is no longer popular and has high availability Be treated as One choice is added to many secondary levels storage system Medium.

However, high availability is in the primary storage Is not an optional option. The ability to read data from a data reduction format (de duplicated or compressed) must exist. In data reduction solutions where de duplication is integrated into Storage array Medium), redundancy Performance is an inevitable result of storage arrays that are almost always highly available.

stay parts In the market de duplication system, a component of the solution sends Client Provide duplicate removal data. This component is called reader. The reader must also be highly available and seamlessly highly available. Some solutions have The server The ability to load the reader on the. Such solutions are often used for near active or more appropriate archive data; They are not suitable for very active data sets.

Most online compression systems are inserted into the system and the network, and placed (logically) Switch And storage between. Therefore, they are achieved due to the high availability that is almost always designed at the network infrastructure level redundancy Sex. Inserting online dedicated equipment along these paths enables seamless failover without extra effort from IT management personnel; It takes advantage of the work already done on the network.

Space saving

Deploying one of these solutions must result in significant capacity Save. If the occupation is reduced capacity Of storage This results in lower than standard user performance, which is of no value.

The primary data is not as high as the backup data usually is redundancy storage pattern. This directly affects the overall capacity Save. There are also two ways to achieve master data reduction: data de duplication and compression.

Data de duplication technology searches for redundancy Data, and what level of data reduction can be achieved will depend on the environment. With high redundancy In a horizontal environment, data de duplication can bring significant ROI ( Return on investment ）In other environments, only 10% to 20% reduction can be achieved.

Compression is effective for all available data, and it can be redundancy While saving more storage capacity, data is also more random Data mode Always bring higher savings.

In fact, the data schema Redundancy The higher the height, the greater the space savings from weight removal. The more random the data mode, the higher the space savings brought by compression.

Application independent

The real benefits may come from all data type Data reduction (no matter what application or how active the data is). Although the actual reduction rate varies according to the level of de duplication data or the compression rate of data, all data must be qualified.

When it comes to archiving or backup, application specific data reduction has clear value, and there is time to customize the reduction process for such data sets. However, for active data sets, the particularity of the application will cause performance bottlenecks and will not bring significant capacity Benefits of reduction.

Storage independent

Use the same data reduction across all platforms in a mixed vendor IT infrastructure tool The ability of will not only further increase the ROI benefits of data reduction, but also simplify deployment and management. every last storage Using a different data reduction method for the platform will require a lot of training and cause confusion at the management level.

complementary

After completing all the above optimizations storage When it is time to back up the primary storage, it is better to keep the data in an optimized format (compressed or de duplicated). If the data must be expanded and restored to the original format before backup, it will be a waste of resources.

To back up an extended dataset, you will need:

use storage Processor or external reader resources decompress data;

extend network resource Take data transfer Give the backup target;

Put extra resource allocation Backup for saving backup data storage device 。

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