The address line is used to transmit address information.To give a simple example, when the CPU looks for a data in the memory or hard disk, it first finds the address through the address line, and then takes the data out through the data line.If there are 32 roots, you can access the 32 power byte of 2, that is, 4GB.
In the address bit multiprocessor protocol (ADDR/IDLEMODE bit is 1), the lastData bitsThere is an additional bit after it, which is called the address bit.The address bit of the first frame of the data block is set to 1, and the address bit of other frames is set to 0.Address bit multiprocessor modedata transmissionAnd[1]data blockThe idle cycles between the two are independent (see Figure Bit 3 in SCICCR register - ADDR/IDLE MODE bit).One address line can only represent 1 and 0.
Transmission principle
Announce
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The value of TXWAKE bit is placed in the address bit. During transmission, when SCITXBUF register and TXWAKE are loaded into TXSHF register and WUT respectively, TXWAKE is cleared to 0, and the value of WUT is the value of the address bit of the current frame. Therefore, the following operations need to be completed to send an address:
1. TXWAKE position 1, write the appropriate address value to the SCITXBUF register.When the address value is sent to the TXSHF register and moved out, the value of the address bit is sent as 1.This allows other processors on the serial bus to read the address.
2. After TXSHF and WUT are loaded, write values to SCITXBUF and TXWAKE (since TXSHF and WUT are double buffered, they can be written immediately).
3. TXWAKE bit remains 0, no address in the sending blockData frame。[2]
Generally, the address bit format shall be used for data frame transmission of 11 bytes or less.This format adds one bit to all data bytes sent (1 represents address frame, 0 represents data frame);Usually 12 or more bytes of data frame transmission uses the idle line format.
(1) Address byte
The first byte of the message sent by the sending node (Talker) is an address byte, which is read by all receiving nodes (Listeners).The receiving node can be interrupted only when the address byte of the received data matches the address byte of the receiving node.If the address of the receiving node does not match the address of the receiving data, the receiving node will not be interrupted and will wait to receive the next address byte.
(2) Sleep bit
All processors connected to the serial bus will use SCI SLEEP position 1 (the second bit of SCICTL1), so that they will be interrupted only after the address byte is detected.When the data block address read by the processor matches the processor address set by the user application software, the user program must clear the SLEEP bit so that the SCI can generate an interrupt when receiving each data byte.
Although the receiver still works at SLEEP position 1, it cannot set RXRDY, RXINT or any receiver error status position 1. These positions can only be set when the address bit is detected and the received frame address bit is 1.SCI itself cannot change SLEEP bit, which must be changed by user software.
(3) Identification address bit
The processor recognizes address bytes in different ways according to the multiprocessor mode used (idle line mode or address bit mode), such as:
● The idle line mode reserves a static space in front of the address byte, and this mode has no additional address/data bits.It is more efficient than address bit mode in processing data block transmission containing more than lO bytes.Idle line mode is generally used for non multiprocessor SCI communication.
● The address bit mode adds an additional bit (that is, address bit) to each byte.Because there is no need to wait between data blocks in this mode, it is more efficient than idle line mode when processing small pieces of data.
(4) Control the characteristics of SCI TX and RX
The user can select the multiprocessor mode through the ADDR/IDLE MODE bit (SCICCR, bit 3) using the software Wu. Both modes use TXWAKE (SCICTL1, bit 3), RXWAKE (SCIRXST, bit 1) and SLEEP flag bit (SCICTL1, bit 2) to control the characteristics of the SCI transmitter and receiver.
(5) Receiving steps
In the two multiprocessor modes, the receiving steps are as follows:
① When receiving the address block, the SCI port wakes up and applies for an interrupt (the RX/BK INT ENA bit of SCICTL2 must be enabled to apply for an interrupt), reads the first frame of the address block, which contains the address of the destination processor.
② Start the software through the address received by interrupt checkroutineAnd then compare the device address stored in the memory with the address byte of the received data.
③ If the above addresses match, the address block matches the address of the DSPCPUClear the SLEEP bit and read the remaining data in the block;Otherwise, exit the software subprogram and keep SLEEP set, and receive the interrupt until the start of the next address block.
