Control bus（ControlBus）It is called CB for short.The control bus is mainly used for transmissioncontrol signalandSequential signal。Some of the control signals are sent tostorageandInput/output deviceInterface circuit, such as read/write signalChip Select 、Interrupt responseSignal, etc;Other components also feed back to the CPU, such as interrupt application signalReset signal, bus request signal, equipment ready signal, etc.Therefore, the transmission direction of the control bus is determined by the specific control signal, which is generally bidirectional. The number of bits of the control bus should be determined according to the actual control needs of the system.In fact, the specific situation of the control bus mainly depends on the CPU.[1]
The control bus is connected together to complete and realize the communication anddata transferOf, soBusThe concept of PC is the basis for understanding the composition, structure, working principle and the relationship between components of PC and motherboard.This control information includes CPU versus memory andI/O interfaceThe input/output interface puts forward theInterrupt requestorDMARequest signals, CPU's response and response signals to these input/output interfaces, various working status signals of input/output interfaces and other various functionscontrol signal。Control bus flows between CPU, memory andInput/output devicebetween.
Control Bus (CB) is characterized by: it is the most complex, flexible and powerful bus in one-way, two-way, dual-mode and other forms, and its number, type and definition are random and different.
classification
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The control bus is a collection of various signal lines and a common channel for transmitting data, address and control information between various parts of the computer.
1. According to the position relative to CPU and its chip:
⑴On chip bus: refers to each internal CPUregister、Arithmetic logic unitALU, control unit and internalCache memoryThe bus used for data transmission between, that is, the chipInternal bus。⑵Off chip bus: The bus (BUS) usually refers to the external bus, which is the CPU and memoryRAM、ROMAnd I/OInput/output deviceData channel for communication between interfaces. The CPU implements program access commands through the bus. Data exchange between memory and peripherals. When the CPU and peripherals are fixed, the bus speed is the biggest factor limiting the overall performance of the computer.
2. By bus function:
⑴Address bus: (AB) is used to pass address information.
⑵data bus: (DB) is used to transfer data information.
⑶ Control bus: (CB) is used to transmit variouscontrol signal。
3. By bus hierarchy:
⑴CPU bus: Including CPUAddress line(CAB), CPU data line (CDB) and CPU control line (CCB), which are used to connect CPU and control chip.
CS31 communication bus
⑵Memory bus: IncludesMemory addressMAB, MDB and MCD are used to connectMemory controller(North Bridge) and memory. ⑶system bus ：（I/OExpansion bus）Also called I/O channel bus or I/O expansion bus, including the systemAddress line(SAB), system data cable (SDB) and system control cable (SCD) are used to connect with various expansion cards on the I/O expansion slot.
⑷External bus: (Peripheral chip bus) used to connect various peripheral control chips, such as I/O controller on the motherboard (such asHard disk interfaceController, floppy drive controller, serial/parallel interface controller, etc.), andKeyboard controller, including external address line (XAB), external data line (XMB), and external control line (XCB).
⒋system bus (I/O) expansion bus) is divided into ISA, PCI, AGP and other standards
⑴ ISA(Industrystandardarchitecture,Industry standard structure）It is a bus industry standard formulated by IBM for 286AT computer, also known as AT standard.
⑵ PCI(peripheralcomponentinterconnet,External equipment interconnection）It was launched by SIG (spelialinterest group)Bus structure。
⑶ AGP(acceleratedgraphicsport，Accelerated Graphics Port）It is a way to improveVideo bandwidthThe designed bus specification is a point-to-point connection, that is, the connection between the control chip and AGP graphics card, so strictly speaking, AGP is also an interface standard.
The bandwidth of the bus refers to the unit timeInternal busThe amount of data uploaded, that is, the maximum steady state of MB transferred per noteData transmission rate。The two factors closely related to the bus areBit widthAnd busworking frequency , their relationship: bus bandwidth=bus operating frequency * bus bit width/8
BusBit widthIt means that the bus can transmit at the same timebinary dataThe number of digits of, ordata busThe number of bits, that is, 32-bit, 64 bit bus width concept.The wider the bit width of the bus, the greater the data transmission rate per secondbandwidthThe wider.
Bus operationclock frequencyIn MHZ, the higher the operating frequency, the faster the bus operates,Bus bandwidthThe wider.
operation
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One operation process of the bus is to complete the transmission of information between two modules. The main module starts the operation process, and the other is the slave module.Only one main module can occupy the bus at a time.[2]
Control bus
Bus operation steps: main module applicationBus control，bus controllerMake a decision.data transferError check of: after the master module gets the bus control rightaddressingSlave module, data transmission is carried out after confirmation of slave module.
Bus timing protocol:Timing protocolIt can ensure that both sides of data transmission operate synchronously and transmit correctly.There are three types of timing protocols:
Synchronous bus timing: all modules on the bus share the same clock pulse to control the operation process.All actions of each module are generated inClock cycleMost actions are completed in a clock cycle.
Asynchronous bus timing: the occurrence of the operation is determined by the specific signal of the source or destination module.The occurrence of an event on the bus depends on the occurrence of the previous event, and both parties provide contact signals to each other.
Control bus model
Bus timing protocol Semi synchronous bus timing: the time interval of each operation on the bus can be different, but it must be an integral multiple of the clock cycle. The appearance, sampling and end of signals are stillCommon clockIs the benchmark.ISA bus adopts this timing method.
Data transmission type: single week mode and burst mode.
Single cycle mode: oneBus cycleOnly one data is transmitted.
Data transmission type:
Burst mode: transmit multiple data after obtaining the control right of the main line.addressingThe first address of the destination is given when accessing the first data. The address from data 2 and 3 to data n is automatically addressed according to certain rules based on the first address (such as automatically adding 1).
standard specification
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Bus is a collection of signal lines, which is a common channel for information transmission between modules. Through it, various data and commands can be transmitted between computer components.In order to make products from different suppliers interchangeable and give users more choices, bus technical specifications should be standardized.
Bus standards should be carefully considered and strictly regulated.Bus standard(Technical Specifications) includes the following parts:
Mechanical structure specification: The module size, bus plug, bus connector and installation size are uniformly specified.
Functional specifications: Each signal line of the bus（PinThe name, function and working process of shall be uniformly specified.
Electrical specification: effective level, dynamic conversion time, load capacity, etc. of each signal line of the bus.
