For the high-performance processor clock system based on CMOS technology, the integrated PLL can be triggered from inside, which is faster and more accurate than triggering from outside, and can effectively avoid some problems related to signal integrity.
Chinese name
System clock
Interpretation
High performance processor based on CMOS technology
Generally speaking, the system clock refers to the clock system, which is a circuit composed of oscillator (signal source), timing wake-up device, frequency divider, etc.Common signal sources are crystal oscillator and RC oscillator.
effect
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The clock is the pulse of the embedded system. The processor core completes instruction execution, state transformation and other actions driven by the clock. Peripheral components complete various tasks driven by the clock, such as serial port data transmission, A/D conversion, timer counting and so on.Therefore, the clock is crucial to the computer system. Usually, problems in the clock system are fatal, such as the oscillator does not start, the oscillation is unstable, and the oscillation stops.
brief introduction
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The following describes the design of a high-performance processor clock system based on CMOS technology. The design frequency is 200MHz, and the phase noise of VCO is-110dBC/Hz@100kHz。The author analyzes the structure and composition of the phase-locked loop in detail, and introduces the design method of eliminating noise.VSPACE=12 HSPACE=12 ALT="Figure 1: Application of PLL in clock generation.
PLL is widely used in clock system design, including phase synchronization and clock frequency multiplication.Usually, when a chipworking frequency When the frequency is higher than a certain frequency, it is necessary to eliminate the phase difference between the on-chip clock and the off chip clock caused by the on-chip clock drive. The PLL embedded in the chip can eliminate this clock delay.In addition, many chip control chain logic requires a clock with a duty cycle of 50%, so a clock with a duty cycle of 2 timesClock sourceThe PLL integrated in the chip can synthesize the external clock as the clock source at this time.
system integration PLL can be triggered internally, which is faster and more accurate than external triggering, and can effectively avoid some problems related to signal integrity.Another notable feature of the system integrated PLL is that it can adjust theClock treeThe parameters in the buffer, and the phase-locked loop can generate relative to the reference inputclock frequencyThis adjustment can ensure the fast synchronization and effective data transmission between the chip and the external interface circuit.
In the design of high performance processor clock system, PLL is usually required to generate on-chip clock.Taking a 200MHz clock system design as an example, this paper introduces a clock system design based on PLL, in which the input reference frequency is 25MHz and the phase noise is-100dBc/Hz@100kHzThe gain of voltage controlled oscillator is 380MHz/V, and the working voltage is 5V.The simulation and test results show that the design can meet the system requirements.
Loop structure
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The clock generation structure based on phase-locked loop is shown in Figure 1: external 25MHz referenceclock signalOr the bus clock (BusCLK) enters a receive buffer first, and passes through a frequency divider before entering the frequency and phase discriminator (PFD). The frequency division coefficient is M1, which is shown in Figure 1φi. Then it is connected with the internal feedback signal from the frequency divider M6ФO Compare in PFD to get error signalФe. It will be used as the input of charge pump and filter network to control voltage controlled oscillator (VCO).VSPACE=12 HSPACE=12 ALT="Figure 2: Phase detector structure.
The output of VCO is first divided by M3, and then buffered to generate the main clock PClk of the system.At the same time, before entering the frequency divider M6, the master clock first passes through the H-tree clock distribution network and finally returns to the phase discriminator, thus forming the entire feedback loop.From the perspective of balance, the two inputs of PFD must be consistent in frequency and phase, so the ratio fpclk/fbus of the chip core clock and the input bus clock obtained must be equal to M6/M1.Input can be obtained by changing the values of M6 and M1clock frequencyInteger times or fractional times of.Since the chip requires that the clock should not drift, the output clock duty cycle and the system's phase adjustment ability must be insensitive to changes in environment and process parameters.The VCO output can also be switched to the frequency divider M5, and the resulting output can be used as the clock of the L2 cache.Similarly, fvco=M3 × fpclk=M5 × fL2CLK. The output frequency of the L2 cache can also be adjusted to an ideal value by adjusting M3 and M1.
Loop composition analysis
The whole loop includes such modules as phase detector, filter, voltage controlled oscillator, frequency divider, common mode suppression and lock detection. The structure of the main modules is described as follows:
The output signal generated by the digital frequency and phase discriminator can express the relative lead or lag information of frequency and phase, and then send it to the charge pump.Reset signalUpon arrival,θEach rising edge of i triggers the "UP" signal untilθWhen a rising edge of o reaches, the setting state of UP will be ended and the system will be reset.Similarly, ifθO The rising edge precedesθWhen i arrives, "DOWN" is set untilθA rising edge of i reaches, and then turns to reset state.Unless the two input phases and frequencies are very close, that is, enter the so-called "phase detection dead zone", the width of the pulse is generally proportional to the difference between the two inputs.The phase detector structure is shown in Figure 2.
2. Voltage controlled oscillator
The voltage controlled oscillator is a key component in the phase-locked loop. There are many structures in practical applications. Figure 3 is a commonly used structure.The D delay unit is the key component of the whole loop, and the selection unit M is responsible for selecting different data channels.
As can be seen from Figure 3, the whole VCO is based on a ring oscillator with an internal delay unit.Compared with the current filled and current modulated VCOs, this kind of differential ring oscillator is widely used in the chip clock generation circuit. At the same time, the VCO with built-in delay unit has relatively low VCO gain, so it is very suitable for differential control and circuit realization on the signal path.Experiments show that the "jitter" of the oscillator with a low gain embedded delay unit is significantly smaller than that of the high gain loop, because the noise is easily decoupled in the low gain structure.Oscillator with built-in delay linkworking frequency Generally, there are certain restrictions. In order to ensure the monotonicity of the loop, the ratio of upper limit to lower limit must be less than 2:1. However, the VCO's operating frequency range can be effectively improved by selecting appropriate frequency divider proportional coefficient or adding programming capability to the VCO's signal path.VSPACE=12 HSPACE=12 ALT="Figure 4: VCO noise curve.
The frequency range of the voltage controlled oscillator depends on the longest and shortest delay on the path, as shown in Figure 3. The peripheral dashed line box represents the route of the maximum frequency fh, which passes through three delay units D and a selection unit M, and the inner dashed line box represents the route of the minimum frequency fl. Its path includes six delay units D and a selection unit M,The selection of different units will also affect the gain of the VCO and the central frequency of the loop.The frequency range can be determined separately by selecting different delay paths with multiple switches, so that the frequency range of VCO can be flexibly adjusted, which is far beyond the frequency range determined by VCO gain.
The delay unit and selection unit in Figure 3 can be built on the basis of PMOS type source coupled differential amplifier with NMOS type load, which can also realize voltage controlled swing adjustment, mainly by adjusting the voltage and changing the payload line.The high resistance state of the current source increases the power noise suppression of the source coupling components. At the same time, the N-well also effectively isolates a large amount of noise on the P-type substrate, increasing the noise suppression performance of the system.
simulation result
Use SpectreRF in Cadence to simulate the designed circuit, and use 0.6μm. 3V/5V, double poly, double metal CMOS process parameters.VCO is a key module in the phase-locked loop. Through PSS and PNoise analysis of VCO, the phase noise figure can be obtained, as shown in Figure 4. The phase noise at 100kHz is approximately - 110dBc/Hz.Figure 5 shows the gain curve of VCO. The gain is about 380MHz/V, with good linearity.
Design summary
Because the phase-locked loop contains analog circuits, noise interference is also a problem that needs to be overcome in the design.The power supply noise generated by the overturning of large digital circuits affects the operation of analog circuits in the phase-locked loopClock cycleIt will change due to the influence of power supply noise or other interference sources (such as thermal noise of MOS tube). It is usually called output "jitter".Clock jitter will directly affect the highest operating frequency of integrated circuits, because it will reduce the available clock cycles.With the reduction of available clock cycles, the digital circuit on the critical path can not get enough time to process data in one cycle, which directly leads to the so-called "critical path error".In addition, the influence of power supply noise is more obvious when there is high power chip interference or mixed signal circuit substrate.VSPACE=12 HSPACE=12 ALT="Figure 5: VCO gain curve.
Frequency deviation at output caused by noise source with frequency of fmΔFout and phase deviationΔθOut can be expressed as
Δθout=Δ
The performance of high-frequency noise and low-frequency noise varies greatly due to their different generation mechanisms, so their suppression methods are different in different applications.Low frequency noise generally includesPower Ripple Random thermal noise of resistor and transistor, random flicker noise of transistor, etc.High frequency noise mainly comes from high-speed flip of digital circuits and fast switching of chip control components. This type of noise is dominant in chip clock design.The phase shift caused by high-frequency noise due to its high frequencyΔθOut is relatively small. Generally, high-frequency noise is described by periodic "jitter".
Classical phase-locked loops contain analog circuits, so they are very sensitive to noise. For on-chip phase-locked loops, the following measures are generally adopted to eliminate noise:
1. Enclose the whole phase-locked loop with power supply and ground wire.The ground coil can keep the substrate potential around the phase-locked loop stable, and a constant substrate potential can suppress noise. Most of the noise introduced by input/output units and other logic circuits is introduced through substrate coupling.
2. Separate the power cord of the phase-locked loop from the power cord of other systems on the chip.The potential of the main power supply is constantly changing due to the instantaneous large current often appearing in the logic circuit or interface circuit.The continuous change of the power supply voltage will affect the noise suppression function of the phase-locked loop. Therefore, when designing the power supply and ground of the phase-locked loop, it should consider separating the main power supply and the phase-locked loop power supply, and using separatePingive.
3. Place the input pin of the phase-locked loop next to the phase-locked loop to prevent it from being affected by power fluctuations and other interferences.
