Concept of bus cycle
one microprocessor Is on clock signal Under CLK control, it works according to the beat. 8086/8088 system clock frequency 4.77MHz, each Clock cycle About 200ns. 2. Because storage and I/O port It is attached to the bus I/O interface The access of is realized through the bus. Usually, the time required for a CPU to access the external part of the microprocessor (memory or I/O interface) through the bus is called a bus cycle. A bus cycle generally includes four clock cycles, which are called four states, namely T1 state, T2 state, T3 state and T4 state. If necessary, one to several Tws can be inserted between T3 and T4. (1) T1 status - output Memory address or I/O address 。 (2) T2 status - output control signal 。 (3) T3 and Tw status - bus operation continues, and READY is detected to determine whether to extend the timing.
(4) T4 status - complete data transfer 。 
