SDRAM

Synchronous dynamic random access memory

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Synchronous dynamic random access memory (SDRAM for short) Synchronization interface Of Dynamic random access memory （ DRAM ）。 Generally, DRAM has an asynchronous interface, so that it can respond to changes in control input at any time. SDRAM has a synchronization interface for response control input Will wait for a clock signal So that we can system bus Synchronization. The clock is used to drive a Finite state machine , execute the incoming command Pipeline (Pipeline) operation. This allows SDRAM to have a more complex operation mode than asynchronous DRAM without synchronous interface.

Pipeline It means that the chip can accept a new instructions 。 In a written Pipeline In, the write command can be executed immediately after another instruction is executed, without waiting for data to be written to the storage queue. In a read pipeline, the required data A fixed number of clock frequencies arrive after the read instruction is issued, and this waiting process can issue other additional instructions. This delay is called latency, which is an important parameter when buying memory for computers.

SDRAM is widely used in computers, from the initial SDRAM to the later generation of DDR (or DDR1), and then DDR2 and DDR3 Entering the mass market, starting from 2015 DDR4 Enter the consumer market.

Chinese name: synchronization Dynamic random access memory
Foreign name: Synchronous Dynamic Random Access Memory

Abbreviation: SDRAM
Features: Synchronous, dynamic, random
Application: FPGA、 Memory

catalog

eight Current mainstream
nine working principle

evolution

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SDRAM has gone through five generations since its development, namely, the first generation SDRAM, the second generation DDR SDRAM, the third generation DDR2 SDRAM, the fourth generation DDR3 SDRAM, the fifth generation DDR4 SDRAM.

The first generation SDRAM adopts single ended clock signal The second, third and fourth generations working frequency It is fast, so the differential clock signal that can reduce interference is used as the synchronous clock.

SDR SDRAM clock frequency It is the frequency of data storage. The first generation memory is named after the clock frequency, such as pc100, pc133 It indicates that the clock signal is 100 or 133MHz, and the data read/write rate is 100 or 133MHz.

The second, third and fourth generation DDR (Double Data Rate) memory uses the data read/write rate as the naming standard, and is preceded by the symbol representing its DDR algebra, PC - that is, DDR, PC2=DDR2，PC3=DDR3。 If PC2700 is DDR333 working frequency Yes 333/2=166MHz, 2700 means bandwidth 2.7G.

The DDR read/write frequency ranges from DDR200 to DDR400, DDR2 from DDR2-400 to DDR2-800, and DDR3 from DDR3-800 to DDR3-1600.

Many people mistakenly interpret SDRAM as the first generation, that is, SDR SDRAM, and as a term, it is misleading.

SDR is not equal to SDRAM.

Pin: the metal pin used for connecting the module or chip with the external circuit, and the pin of the module is often referred to as the "golden finger".

SIMM：Single In-line Memory Module, Single row memory module. Memory module is what we often say Memory module The so-called single row means that there is only one row of interfaces between the module circuit board and the motherboard slot Pin (Although there are golden fingers on both sides).

DIMM：Double In-line Memory Module， Dual rank memory module. It is a common module type. The so-called double row means that the interface between the module circuit board and the motherboard slot has two rows of pins, and the gold fingers on both sides of the module circuit board correspond to a row of pins.

RIMM：registered DIMM， A dual line memory module with registers. This memory slot can only insert DDR or Rambus memory.

SO-DIMM : The common memory module of the notebook.

Operating voltage:

SDR：3.3V

DDR：2.5V

DDR2：1.8V

DDR3：1.5V

DDR4：1.2V

SDR SDRAM memory The golden finger of a line is usually 168 lines, while DDR SDRAM Memory module The golden finger is usually 184 lines.

The number of notches and the position of the notches of several generations of golden fingers are also different to effectively prevent reverse and wrong insertion. SDR SDRAM has two notches and DDR has only one.

relationship

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Relationship between structure, timing and performance

1、 Main timing parameters affecting performance

The so-called performance impact does not refer to SDRAM bandwidth , Frequency vs Bit width Once fixed, the bandwidth cannot be changed. But this is an ideal situation. During the working cycle of memory, it is impossible to always be in the state of data transmission, because there must be commands addressing And other necessary processes. However, the shorter the time taken for these operations, the higher the efficiency of memory work, and the better the performance.

The main components of non data transmission time are various delays and latency. From the above description, it should be obvious that there are three parameters that have a critical impact on memory performance: tRCD, CL, and tRP. Each regular memory module will be marked with these three parameter values on the label, which shows their sensitivity to performance.

Take reading, the main operation of memory, as an example. TRCD determines the interval between row addressing (effective) and column addressing (read/write commands), CL determines the time it takes from column addressing to data being actually read, and tRP determines the speed of conversion between different working lines in the same L-Bank. Now you can imagine several situations that may be encountered when reading (just do not consider CL when analyzing write operations):

1. The line to be addressed and L-Bank are free. That is to say, all the lines of the L-Bank are closed. At this time, you can directly send the effective command of the line. The total time before data reading is tRCD+CL, which is called page hit (PH, Page Hit).

2. The line to be addressed is exactly the working line of the previous operation, that is, the line to be addressed has been in the strobe valid state. At this time, the column addressing command can be sent directly, and the total time before data reading is only CL, which is called back to back addressing. We call it page fast hit or page direct hit, Page Direct Hit）。

3. A line in the L-Bank where the line to be addressed is located is already active (not closed). This phenomenon is called addressing conflict. At this time, you must pre charge to close the work line, and then send a valid command to the new line. As a result, the total time consumption is tRP+tRCD+CL, which is called page miss (PM).

Obviously, PFH is the best addressing situation, and PM is the worst addressing situation. The probability of the above three situations is called PHR for short - PH Rate PFHR——PFH Rate、PMR——PM Rate。 Therefore, system designers (including memory and Beiqiao chip ）Both want to improve PHR and PFHR as much as possible, and reduce PMR at the same time to achieve the purpose of improving memory efficiency.

2、 Ways to increase PHR

Obviously, this is directly related to the pre charge management strategy. At present, there are two ways to improve PHR as much as possible. Automatic pre charging technology is one of them. It automatically pre charges after each line operation, thus reducing the possibility of conflict when addressing the same L-Bank with different lines in the future. However, if you want to open another line of the same L-Bank immediately after the current line is completed, there is still a delay of tRP. What should I do? At this point, L-Bank interleaved pre charging is required.

VIA's 4-way interleaved memory control is to precharge the next L-Bank to work when one L-Bank is working. In this way, the pre charging and data transmission are interleaved. When the next L-Bank is accessed, the tRP has passed, and you can directly enter the effective state of the line. At present, VIA claims that it can carry out 16 routes across P-Bank Memory interleaving And carries out pre charging management with LRU algorithm.

The specific implementation of L-Bank interleaving pre charge (access) has been introduced in detail in the second issue of this journal in 2001, and will not be repeated here.

L-Bank interleaved automatic pre charge/read Sequence diagram (Click to zoom in): L-Bank 0 and L-Bank 3 realize interlaced reading without gaps, avoiding the impact of tRP on performance.

3、 Ways to increase PFHR

Neither automatic pre charging nor interleaving can eliminate the delay caused by tRCD. To solve this problem, it is necessary to make one work line receive as many work commands as possible before precharging to achieve the back-to-back effect. At this time, only the read delay caused by CL is left (there is no delay when writing).

How to do this? This is it. Beiqiao chip Is responsible for. In the above Sequence diagram There is a parameter tRAS (Active to Precharge Command, the line is valid until the interval period of the precharge command). It has a range. For the PC133 standard, the precharge command should be at least 5 valid commands on the line Clock cycle After that, the maximum interval varies according to the chip (basically around 120000ns), otherwise the data in the work line will be lost. This means that a working line can have a continuous working time of 120000ns without precharging from the effective (strobe) start. Obviously, as long as the Beiqiao chip does not issue the command of pre charging (including allowing automatic pre charging), the line will remain open. During this period, there will be no tRCD delay for any read/write operations on this line. It can be seen that if the North Bridge chip can open more lines (pages) at the same time, the PFHR will be larger. It should be emphasized that simultaneous opening here does not mean addressing multiple lines at the same time (that is impossible), but means that multiple lines are in gated status at the same time. We can see some SDRAM Chipset The index of how many pages can be opened at the same time will be indicated in the information of. This can be said to be an important factor in determining its memory performance.

Information about Intel 845 chipset MCH: It shows that it can support 24 pages to be opened at the same time

However, there is a limit to the number of pages that can be opened at the same time. From the addressing principle of SDRAM, it is impossible to have two open rows in the same L-Bank (S-AMP can only serve one row), which limits the total number of pages that can be opened at the same time. Taking SDRAM as an example, there are 4 L-Banks and Beiqiao supports at most 8 P-Banks. Theoretically, only 32 pages can be opened at the same time. If there is only one P-Bank, there are only four pages left, because only several L-Banks can open several lines at the same time without interfering with each other. Although the MHC of Intel 845 can support 24 open pages, that means 6 P-Banks (845MCH only supports 6 P-Banks). It can be seen that 845 has brought the number of pages opened at the same time into full play.

However, more pages are opened at the same time, which also puts forward certain requirements for the access strategy. In theory, open pages should be used as much as possible to ensure the shortest delay period. Only when data does not exist (when reading) or Page storage When the page is full (when writing), consider opening a new specified page, which is also called continuous read/write with changing direction. When you open a new page, you must close an open page. If the opened page is already the maximum supported by Beiqiao, but it does not reach the theoretical limit, you need a replacement strategy, which generally uses the LRU algorithm, which is similar to the interleaving control of VIA.

Specifications

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Chips and modules

Standard name	Memory clock	cycle	I/O bus clock	Data rate	transmission mode	module name	Limit transmission rate
DDR-200	100MHz	10ns	100 MHz	two hundred Million	parallel transmission	PC-1600	1600MB/s
DDR-266	133 MHz	7.5 ns	133 MHz	266 Million	parallel transmission	PC-2100	2100 MB/s
DDR-333	166 MHz	6 ns	166 MHz	333 Million	parallel transmission	PC-2700	2700 MB/s
DDR-400	200 MHz	5 ns	200 MHz	400 Million	parallel transmission	PC-3200	3200 MB/s

Memory chip

DDR-200: DDR-SDRAM memory chip runs at 100MHz

DDR-266: DDR-SDRAM memory chip runs at 133MHz

DDR-333: DDR-SDRAM memory chip runs at 166MHz

DDR-400: DDR-SDRAM memory chip operates at 200MHz (the highest specification of DDR formulated by JEDEC)

DDR-500: DDR-SDRAM memory chip operates at 250MHz (not the DDR specification formulated by JEDEC)

DDR-600: DDR-SDRAM memory chip operates at 300MHz (not the DDR specification formulated by JEDEC)

DDR-700: DDR-SDRAM memory chip operates at 350MHz (not the DDR specification formulated by JEDEC)

Chip module

PC-1600 memory module refers to DDR-200 working at 100MHz Memory chip , which has 1.600GB/s bandwidth

PC-2100 memory module refers to the DDR-266 memory chip operating at 133MHz, which has a bandwidth of 2.133GB/s

PC-2700 memory module refers to the DDR-333 memory chip operating at 166MHz, which has a bandwidth of 2.667GB/s

PC-3200 memory module refers to a DDR-400 memory chip operating at 200MHz, which has a bandwidth of 3.200GB/s

formula

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DDR SDRAM time pulse can be calculated by using the following formula.

DDR I/II memory operation time pulse: actual time pulse * 2. (Since the data on both sides are transmitted at the same time, the clock of 200MHz memory will operate at 400MHz.)

Memory bandwidth = Memory speed * Memory bit width

Standard formula: memory frequency division coefficient=time pulse/200 → * quick calculation method: fsb *(division frequency/synchronization frequency) (using this formula will result in an error of 4%)

address-of

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(1) Bank block address --- locate logical block

（2） Line Address And column address --- positioning Storage unit

Capacity definition

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Capacity definition: number of addresses* Bit width *Bank (storage block).

Pin introduction

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SDRAM pays attention to the following signals when reading and writing data:

（1）CLK： clock signal , is the input signal. The logic states of all input signals of SDRAM need to be determined by sampling the rising edge of CLK.

(2) CKE: clock enable signal, which is an input signal and is effective at high level. CKE signal has two purposes: first, turn off the clock to enter the power saving mode; 2、 Enter the self refresh state. When CKE is invalid, all input related functional modules in SDRAM stop working.

（3）CS#： Chip Select , is the input signal, Active at low level 。 Only when the chip selection signal is valid can SDRAM recognize the command sent by the controller. Pay attention to pull up during design.

（4）RAS#： Line Address The strobe signal is an input signal, which is effective at low level.

(5) CAS #: column address strobe signal, which is an input signal and effective at low level.

(6) WE #: Write enable signal, which is an input signal and is valid at low level.

Of course, it also includes bank [...] address signal, which needs to be determined according to different models. It is also an input signal; Address signal A [...] is the input signal; Data signal DQ [...] is input/output bidirectional signal; The data mask signal DQM is an input/output bidirectional signal with the same direction as the data flow, and the high level is valid. When it is valid, data bus The corresponding data bytes on the are shielded by the receiving end.

Current mainstream

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DDR3 memory 。 It belongs to the memory product of SDRAM family, providing higher operating efficiency and lower voltage than DDR2 SDRAM. It is DDR2 SDRAM (quadruple data rate synchronization Dynamic random access memory ）It is also a popular memory product.

DDR3 SDRAM transmission efficiency Faster. I/O interface of SSTL 15 is used. The operating I/O voltage is 1.5V. CSP FBGA package In addition to continuing the ODT, OCD, Posted CAS, and AL control modes of DDR2 SDRAM, more advanced CWD, Reset, ZQ, SRT, and PASR functions are added to the mode packaging.

CWD is used as a write delay. Reset provides the command of super power saving function, which allows DDR3 SDRAM Memory granule When the circuit stops operation and enters the ultra power saving standby mode, ZQ is a new terminal resistance calibration function. The new line pin provides ODCE (On Die Calibration English) to calibrate ODT (On Die Termination) Internal interrupt SRT (Self Refresh Temperature) programmable temperature control memory clock function is added, The addition of SRT optimizes the memory particles in terms of temperature, time pulse and power management. It can be said that within the memory, the power management function is done, and the stability of the memory particles is greatly improved to ensure that the memory particles will not be burned due to too high working time pulse. At the same time, DDR3 SDRAM also adds the function of PASR (Partial Array Self Refresh) local bank refresh, It can be said that more effective data reading and writing can be done for the entire memory bank to save power.

working principle

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SDRAM becomes DRAM because it needs to refresh continuously to retain data, because refresh is the most important operation of DRAM. Then how often should the data be refreshed again? The currently recognized standard is that the upper limit of the effective storage period of the capacitance data in the memory is 64ms (milliseconds, 1/1000 seconds), that is, the cycle period of each row is 64ms. The refresh speed is 64ms/line number. When we look at the memory specifications, we often see the 4096 Refresh Cycles/64ms or 8192 Refresh Cycles/64ms logo. The 4096 and 8192 here represent the number of rows per bank in the chip. The refresh command is valid for one line at a time, and the transmission interval also varies with the total number of lines. It is 15.625 μ s (microseconds, 1/1000 ms) for 4096 lines and 7.8125 μ s for 8192 lines. HY57V561620 is 8192 refresh cycles/64ms.

SDRAM is a multi bank structure. For example, in a module with SDRAM for two banks, one bank can be read immediately while the other bank is precharging. In this way, when the data of the precharged bank is read immediately after a read, it can be read directly without waiting, which is greatly improved storage Access speed of.

To achieve this function, SDRAM needs to increase the management of multiple banks to control the pre charging of banks. In an SDRAM with more than two banks, there is usually an additional one called BAn Pin , which is used to select between multiple banks.

SDRAM has multiple working modes, and its internal operation is complex State machine 。 The pins of SDRAM devices are divided into the following categories.

（1） control signal : Includes Film selection , clock, clock enable, row and column address selection, read/write valid and data valid.

(2) Address signal: TDM pin, select pin according to row and column address, and control input address is Line Address Or list the address..

(3) Data signal: bidirectional pin, effectively controlled by data.

All SDRAM operations are synchronized to the clock. Various input commands can be generated according to the status of the rising edge of the clock to control pins and address inputs.

pattern register Set command.

Activate the command.

Precharge command.

Read commands.

Write commands.

Read command with pre charge.

Write command with pre charge.

Automatic refresh command.

Self refresh command.

Sudden stop command.

Empty operation command.

According to the input command, SDRAM status is transferred between internal states. Internal status includes mode register Set status, activation status, pre charge status, write status, read status, pre charge read status, pre charge write status, auto refresh status, and self refresh status.

SDRAM supports the following operation commands: initialization configuration, pre charging, line activation, read operation, write operation, automatic refresh, self refresh, etc. All operation commands pass through control lines CS #, RAS #, CAS #, WE # and Address line . Body selection address BA input.

1. Row activation

The line activation command selects any line of the memory in the idle state to enter the ready read/write state. The number of clock ticks between slave activation and allowed input of read/write commands depends on the internal characteristic delay and clock frequency 。 HY57V561620 has four individuals inside. In order to reduce the number of device gates, some circuits between the four individuals are common, so they cannot be activated at the same time, and there must be a certain time interval between the activation of one individual and the activation of another.

2. Precharge

The precharge command is used to precharge the active line to end the active state. The precharge command can be applied to a single entity or all entities at the same time (through the precharge command of all entities). For the burst write operation, it must be ensured that the write operation has been completed before the pre charge command is written, and DQM is used to prohibit further data writing. After the pre charge is completed, it returns to the idle state and can also be activated again. At this time, you can also enter the operation commands such as entering low power consumption, automatic refresh, self refresh and mode setting.

The rewriting operation in precharge is the same as the refresh operation, except that precharge is not scheduled, but only performed after the read operation. Because the read operation will destroy the charge in the memory. Therefore, the memory should not only be refreshed every 64ms, but also refreshed after each read operation.

3. Automatic pre charge

If the A10/AP position is "1" in the burst read or write command, a precharge action will be automatically attached after the read/write operation is completed. The operation line ends the active state, but is internal State machine New operation commands cannot be sent to the device before returning to the idle state.

4. Burst reading

The burst read command allows several data to be read continuously after one line of an individual is activated. The first data is displayed on the data line after the specified CAS delay beat, and a new data will be read out at each clock beat. The burst read operation can be suspended by the new burst read/write command of the same or different body, or the pre charge command and the burst stop command of the same body.

5. Burst writing

The burst write command is similar to the burst read command, which allows several data to be written consecutively after a line in an individual is activated. The first write data and burst write command are given on the data line at the same time, and a new data is given at each clock beat later. The input buffer stops receiving data after the burst data volume meets the requirements. Burst write operation can be aborted by burst read/write command or DQM data input mask command and pre charge command or burst stop command.

6. Auto refresh

because Dynamic memory Storage unit There is leakage. In order to keep the data of each storage unit correct, HY57V561620 must ensure that all storage units are refreshed within 64ms. An automatic refresh cycle can only refresh one row of the storage unit. After each refresh operation, the internal refresh address counter automatically adds "1". The automatic refresh operation can only be started when all bodies are idle (because the corresponding rows of the four bodies are refreshed at the same time) and are not in the low power consumption mode. During the execution of the refresh operation, only empty operations can be entered. After the refresh operation is completed, all bodies enter the idle state. The device can execute an automatic refresh command every 7.8 μ s, or refresh all units in a centralized manner within a certain time period of 64ms.

7. Self refresh

Self refresh is Dynamic memory Another refresh mode of, usually used to maintain SDRAM data in low power consumption mode. In the self refresh mode, SDRAM disables all internal clocks and input buffers (except CKE). In order to reduce power consumption, the refresh address and refresh time are all generated inside the device. Once entering the self refresh mode, it can only be activated when the CKE is lowered, and any other input will not work. After the command of withdrawing from the refresh mode is given, the empty operation input of a certain beat must be maintained to ensure that the device finishes withdrawing from the refresh mode. If the centralized automatic refresh mode is used during normal operation, the centralized automatic refresh operation (8192 for HY57V561620) must be performed once after exiting the self refresh mode.

8. Clock and clock mask

clock signal It is the synchronous signal of all operations, and the rising edge is valid. The clock mask signal CKE determines whether to apply the clock input to the internal circuit. During the read/write operation, the output state and burst address are frozen at the next beat after the CKE becomes low until the CKE becomes high. When all the bodies are in the idle state, SDRAM enters the low power consumption mode at the next beat after the CKE becomes low and remains high until the CKE becomes high.

9. DQM Operation

DQM is used to shield input and output operations. For output, it is equivalent to door opening signal. For input, it is prohibited to write data on the bus Storage unit 。 DQM delay of read operation is 2 Clock cycle It starts to work. For write operations, it is effective on the beat.^[1]

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