Considering the real-time and reliability requirements of the test systemEthernetPort as a data transmission bus converter andUpper computerHigh speed serial port is used as the control port, and FPGA+DSP+ARM architecture is used as the real-time information processing platform.
The system block diagram of the data transmission bus converter is shown in Figure 1.Among them, FPGA serves asData preprocessingTo complete data pre-processing tasks such as conversion of parallel data to serial data;DSP reads the data processed by FPGA and completes the task of data compression;As the central processing controller, ARM mainly reads the encoded data from the DSP system and completes the real-time communication with the host computer through the Ethernet port.The upper computer demodulates various physical variables according to the data transmission protocol and the product data telemetry protocol, records and stores them.Testers passedUpper computerComplete remote control of working status and various information interaction tasks.The high-end architecture of FPGA+DSP+ARM is adopted in the system, but the overall performance of a system depends not only on the devices used and the functions completed, but also on the interface forms between various devices.On the information processing platform of FPGA+DSP+ARM, the interface form between the three will determine the performance of the entire system.To meet real-timesignal processing Task, selectDSP chipIn addition to the processing speed of the DSP chip, the interface capability between the DSP chip and FPGA and ARM should also be considered. The DSP with EMIF and HPI interfaces should be selected to make it seamlessly connected with FPGA and ARMsystem designThe key link of.
2、 Device selection
Announce
edit
In the data transmission bus converter, the XC3S500E in the low-cost field programmable gate array Spartan-3E series newly launched by Xilinx Company is selected as the FPGA.XC3S500E contains 20 block RAM, 18 KB modules in each RAM blockstorageIs a fully synchronized, true dual ended memory.Users can read from or write to each port independently (but the same address cannot be read and written at the same time).In addition, each port has an independent clock, and the data width of each port can be configured independently.
The ARM chip is S3C4510B from Samsung.S3C4510B is based onEthernetThe high cost performance 16/32 bit RISC microcontroller of the application system contains a 16/32 bit ARM7TDMI RISC processor core designed by ARM.In addition to the ARM7TDMI core, the S3C4510B also has many important peripheral function modules, including oneEthernet controller, used for network communication between S3C4510B system and other devices [1].
DSP chip is made of TITMS320C6416。TMS320C6416 is a high-speed fixed-point DSP launched by TI Company. It has a powerful CPU, up to 1 MB of RAM, richPeripheral Interface 。Peripherals including CPU accessPeripheralsFlexible external for seamless interfacestorageInterfaces EMIFA and EMIFB, a PCI interface that makes it easy for DSP to seamlessly connect to an external main CPU with PCI function through PCI interface, and a 16/32 bit wide asynchronous parallel interface HPI (the same as PCIPin）, an enhanced version that provides 64 bit data channel accessEDMAEtc.Its high-speed processing speed meets the real-time requirements of the system, and can realize seamless connection with a variety of peripherals.
3、 System software design
Announce
edit
3.1 Embedded operating system
In this data transmission bus converterdata compressionThe task of is completed by DSP.The ARM S3C4510B completes the Ethernet communication with the PC, and the real-time, reliability and complexity required by the software implementation make it possible to choose aEmbedded real-time operating systemAnd μ CLinux is an operating system with complete TCP/IP protocol. Real time is added to μ CLinuxRT-LinuxModule to meet the requirements forEmbedded operating systemReal-time requirements.
3.2 Baseband, frequency band and digital data transmission
① Baseband transmission is defined asData terminal equipment(DTE) The transmission mode in which the electrical signal of binary "1" or "0" sent out is directly sent to the circuit.Without modulation, baseband signal can be directly transmitted after being driven by code shape transformation (or waveform transformation).The characteristic of baseband signal is that there are DC, low-frequency and high-frequency components in the spectrum. As the frequency increases, its amplitude decreases accordingly, and finally tends to zero.Baseband transmission is mostly used in short distance data transmission, such as short distance computer to computerdata communicationOr in LANTwisted pairorCoaxial cableData transmission for media. ②Most transmission channels are band-pass, and baseband signals cannot pass.The modulation method is used to modulate the baseband signal to the channel bandwidth for transmission, and the receiver restores the baseband signal through demodulation method, which is called frequency band transmission.This way can realize long-distance data communication, for example, using the telephone network can realize nationwide or global data communication. ③Digital data transmission is a way to transmit data signals using digital voice channels.For example, with PCM（Pulse code modulation）The digital telephone channel can transmit 64kbit/s data signal without modulation, with high efficiency and good transmission quality. It is a good transmission mode for data communication.
3.3 Parallel transmission and serial transmission
① Parallel transmission is to form charactersBinary codeThe mode of simultaneous transmission on parallel channels.For example, 8 unit code characters need to be transmitted simultaneously through 8 channels in parallel. One character is transmitted at a time. There is no synchronization problem between the receiving and sending sides, and the speed is fast. However, there are many channels and large investment, so data transmission is rarely used. ②Serial transmission refers to the way that binary code is transmitted bit by bit in chronological order on a channel.Send by bit, receive by bit, and confirm characters at the same time, so synchronous measures should be taken.Although the speed is slow, only one transmission channel is needed, with small investment and easy implementation. It is the main transmission mode used for data transmission.
3.4 Asynchronous transmission and synchronous transmission
① Asynchronous transmission is the synchronous transmission of characters, also known as start stop synchronization.When sending a character code, a "start" signal shall be added in front of the character, with a length of 1SymbolWide, polarity is "0", that is, empty number polarity;After sending a character, add a "stop" signal with a length of 1, 1.5 (for international code 2) or two symbol widths, and the polarity is "1", that is, the polarity of the transmission signal.The receiving end can distinguish the transmitted characters by detecting the start and stop signals.characterIt can be sent continuously or separately. When no characters are sent, the stop signal is sent continuously.The starting time of each character can be arbitrary, the length of code elements within a character is equal, and the receiving end detects the beginning of a new character through the jump from stop signal to start signal ("1" and "0").This method is simple, and the receiver and senderclock signalPrecise synchronization is not required.The disadvantage is that the start and stop signals are added, and the efficiency is low. It is used in low speed data transmission.
② Synchronous transmission is bit（Symbol）Synchronous transmission mode.In this way, accurate bit timing signals must be established on both the receiving and sending sides to correctly distinguish each data signal.In transmission, data shall be divided into groups (or frames), and a frame contains multiple character codes or multiple independent symbols.Before sending data, the specifiedFrame synchronizationAfter the receiver detects the sequence mark of the symbol sequence, it determines the start of the frame and establishes synchronization between the two sides.The receiving DCE extracts the bit timing signal from the receiving sequence to achieve bit (symbol) synchronization.Synchronous transmission without start and stop signals,transmission efficiency High, used for data transmission above 2400 bit/s, but the technology is complex.
3.5 Simplex, half duplex and full duplex transmission
Simplex transmission means that data can only be sent and received in a single direction;Half duplex transmissionIt refers to that data can be transmitted in two directions but not simultaneously, i.e. alternately receiving and transmitting;Full duplex transmission means that data can be transmitted in two directions simultaneously, that is, simultaneously received and sent.Generally, four wire lines are full duplex data transmission, and two wire lines can realize full duplex data transmission.
3.6 Wireless data transmission service
Wireless data transmissionThe service refers to the end-to-end data transmission service provided in a wireless manner that is not included in the aforementioned basic telecommunications service entries. The service can provide roaming services, which are generally regional.
The systems providing such services includeCellular dataGrouping data(CDPD), PLANET, NEXNET, Mobitex and other systems.Bidirectional paging is an application of wireless data transmission service.
The operator of wireless data transmission service must set up a wireless data transmission network by itself. The operator without the right to operate domestic communication facilities service business shall not build domestic transmission network facilities, and must rent the transmission facilities of the operator with the corresponding right to operate to set up a business network.
Data transmission rate refers to the speed of data transmission between MO magnetic disc drive and host, in MB/s.Data transfer rate is an important parameter to measure the performance of MO magneto-optical disk drive.The higher the data transfer rate, the higher the performance of the MO magneto-optical disk drive.The data transmission rate can be divided into pulse transmission rate and sustained transmission rate. The sustained transmission rate really reflects the actual performance of the MO magneto-optical disk drive.At present, the data transmission rate of mainstream products is between 4MB/s-10MB/s.
3.7 Driver and application development
The development of hardware drivers and applications based on μ CLinux operating system isCross compilation environmentFirst, it is developed on a PC, then transplanted to the target machine for debugging and finally solidified to the target machine.The developed hardware drivers areEthernetCard controller driver, LCD driver, HPI driver and other drivers.The system software structure is shown in Figure 4
stayμClinuxThere are three tasks running on the operating system: reading compressed data, sending data through Ethernet, receiving and executing commands from remote PCs.Among them, the task of reading DSP compressed data requires real-time performanceInterrupt processingThe other two tasks are implemented through user processes.The Ethernet task of sending data and the task of reading compressed data share a buffer, and the buffer is passed between them through the ioctl functionDouble linked listAddress of.Therefore, it is necessary tocommunication interfaceHPI registers a driver with the following functions:
result=register_chrdev(HPI_MAJOR,"hpi",&hpi_fops)
The main structure of the driver is as follows:
struct file_operations hpi_fops=
{
owner: THIS MODULE,
open: hpi_open,
read: hpi_read,
write: hpi_write,
ioctl: hpi_ioctl,
mmap:hpi_mmap,
release:hpi_release,
};
After the HPI driver is written, place the driver source code in/Linux-2.4.x/driver/char directory, and modify the Makefile in the same level directory/Add Obj_y+=hpi in linux-2.4. x/driver/char/Makefileo
At the same time, in order to be able to access the information in the "?Initialize this automatically when Clinux startsCharacter device, you need to modify/Linux-2.4.x/driver/char/men.c file, add:
(1) The newly added character driver initialization function declaration: extern void hpi_init (void);
(2) To call the initialization function of a new device in the unified initialization function int _init chr_dev_init (void) for character devices, you need to add the statement hpi_init() in int _init chr_dev_init (void);
In the function int _init chr_dev_init (void),Character deviceThe initialization function of will be called uniformly, and the registration of the character driven file_operations data structure will be completed. After initialization, the HPI character device can be used.
The data transmission bus converter designed in this paper not only solves the problem of signal distortion caused by long transmission distance, but also meets the real-time requirements of information transmissiongatewayFunction and embedded Web function can ensure that the system can access the Internet safely.
4、 Data transfer program
Announce
edit
orihi equ 10H ;Source high 8-bit address
ORILO EQU 00H ;Source 8 low order address
TARHI EQU 20H ;Destination high-8 address
TARLO EQU 00H ;Destination low 8-bit address
CONHI EQU 01H ;8 bits higher than the number of bytes
CONLO EQU 0FFH ;Byte number 8 bits
ORG 0000H
LJMP MAIN
MAIN:
setb rs0
setb rs1
MOV R2, #ORIHI
MOV R3, #ORILO
MOV R4, #TARHI
MOV R5, #TARLO
MOV R6, #CONHI
MOV R7, #CONLO
MOV DPH, R2;Place the high bit address of the source in the high bit of the DPTR
MOV DPL, R3;Place the low order address of the source in the low order of the DPTR
PUSH DPL；Pointer variable is pushed to the stack at a low position
MOV DPH, #58H；Take the external 5800H high eight bit address and send it to the pointer variable high eight bit address
MOV DPL, R1；Modify the low eight bits of pointer variable
MOVX @DPTR,A；data transfer
POP DPL；Pop up pointer variable low order
POP DPH；Pop up pointer variable high order
INC DPTR；Modify pointer variable
INC R1
DJNZ R2, LOOP4；Whether the cycle ends is to continue, otherwise, the cycle
MOV R2, #10H；Initialization cycle control quantity
MOV DPTR, #5800H；Get the external address 5800H toPointer variable
MOV R0, #50H；Address in chip removed 50H
LOOP5: MOVX A, @DPTR
MOV @R0, A;data transfer
INC R0；
INC DPTR；
DJNZ R2, LOOP5；Whether the cycle ends is to continue, otherwise, the cycle
END
6、 Hardware design
Announce
edit
DSP TMS320C6416 HPI description
TMS320C6416 is integrated with a 16/32 bit wide host interface HPI. The HPI passes the bootstrap and device configuration during resetPinHD5 selects HPI16 or HPI32.HPI has twoAddress lineHCNTRL [1:0], responsible for the internal management of HPIregisterAddresses.HPI has only three 32 bit internal registers, which areControl registerHPIC、Address registerHPIA andData registerHPID。Users only need to read and write the three registers mentioned above to complete the access to the DSP memory space [2].
Interface circuit between S3C4510B and TMS320C6416
Since there is no external interface in S3C4510B that completely conforms to the timing of the TMS320C6416 HPI interface that can be used directly, the external I/O interface in S3C4510B with the timing closest to the timing of the HPI interface and the TMS320 are selected-
C6416.The interface circuit between TMS320C6416 and S3C4510B is shown in Figure 2.TMS320C6416 and S3C4510B pass through separate 32 bit data cableHD0~HD31 and 8 control lines.The S3C4510B accesses the internal RAM and other external resources of the DSP through the HPI interface.In the whole process of communication and data exchange between ARM microprocessor and DSP chip through HPI interface, except for interrupting ARM and clearing interrupts sent by ARM, DSP itself is required to participate in other operations, and DSP is in a passive position, almost no other operations are required.So for ARM, the DSP system unit is equivalent to an external SDRAM.
In TMS320C6416, HPI, GP [15:9], PCI, EEPROM, and McBSP2 share a set of pins. When resetting, the DSP selects which peripheral to use by locking the values of PCI_EN and McBSP2_EN pins.In this system, pull down both enable pins.
