When an ordinary modern computer is turned on, it willPower on self-test（POST）。Since the mid-1990s, this process has included automatically configuring existing hardware.SPD is a memory hardware feature that enables the computer to understand the existing memory and the memory accesssequential。
Some computers can fully and automatically adapt to hardware changes.In most cases, there is a special optional step that can be accessedBIOSParameters, can be viewed and relevant settings may be changed.Some computers can control how to use the data stored in SPD - can selectively modify the memory timing, or even completely cover (ignore) the SPD data, seeOverfrequency。
When the computer is powered on, the serial presence detection (SPD) is stored in synchronizationDynamic random access memory(SDRAM) memory module, electrically erasable programmable read-only memory (EEPROM) chip.[1]
Stored information
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For memory modules that support SPD,JEDECThe standard requires that aEEPROMThere are specific parameters in the lower 128 bytes on the.These bytes include timing parameters, manufacturer, serial number and other practical information related to the module.The device using memory can read this information to automatically determine the key parameters of the module.For example,SDRAMThe SPD data on the module may provide information aboutCAS latencyThe system can be automatically configured without user intervention.
SPD EEPROM adoptsSMBusAccess, this isI²CA variant of the protocol.This reduces the number of communication pins on the module to two: clock signal and data signal.EEPROM shares ground pin with RAM, has its own power pin, and has three additional pins (SA0-2) to identify the slot, which is used to assign EEPROM to a unique address in the range of 0x50-0x57.The communication line can be shared between eight memory modules. The same SMBus is usually used for system health monitoring tasks on the motherboard, such as reading the power supply voltageCPU temperatureAnd fan speed.
(If there is no write protection, SPD EEPROMs also respond to I ² C address 0x30 – 0x37.An extension uses the 0x18 – 0x1F address to access the optional chipTemperature sensor。）[2]
SDR SDRAM
The first SPD specification was issued by JEDEC and strengthened by Intel as itsPC100Part of the memory specification.Most values specified areBinary decimalForm.Most importantHalf byteIt can contain 10 to 15 values, and in some cases can be expanded to higher values.In this case, the encoding of 1, 2 and 3 is used for encoding 16, 17 and 18.The half byte of the highest 0 is reserved for "undefined".
SPD ROM defines up to three DRAM time sequences, and specifies three CAS delays with the setting bit in byte 18.The first is the highest CAS latency (the fastest clock), and then the two lower CAS latencies that reduce the clock speed.[1]
DDR2 SDRAM
Some modifications have been made to the DDR2 SPD standard, but generally the same as above.One notable change is to remove the messy and rarely used DIMM support with two Ranks of different sizes.[2]
DDR3 SDRAM
DDR3 SDRAM standard has been greatly improved, simplifying the layout of SPD content.Instead of nanosecond fields encoded by multiple BCDs, some "time base" units are specified as high-precision, and various timing parameters are encoded as multiples of basic units.In addition, the practice of specifying different timing according to CAS delay has been deleted, and now there is only one set of timing parameters.
Revise 1.1 to express some parameters as "medium time base" value plus (with sign, - 128+127) "fine time base" correction.Generally, the medium time base is 1/8 ns (125 ps), and the fine time base is 1, 2,5 or 5 ps.For compatibility with earlier versions that lack correction, the medium time base is usually rounded up and the correction is negative.The values that work in this way are:
The storage capacity of the module can be calculated from bytes 4, 7 and 8.The module width (byte 8) is divided by the number of bits per chip (byte 7) to get the number of chips per rank.Then it can be multiplied by the capacity of each chip (byte 4) and the number of chips on the module (usually 1 or 2, from byte 7).[2]
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JEDEC standard only specifies some SPD bytes.The truly critical data is placed in the first 64 bytes, while the rest is calibrated by the manufacturer.However, the EEPROM provided is usually 256 bytes.The remaining space has some uses at present.
Enhanced Performance Configuration (EPP)
The memory usually has conservative timing recommendations in the SPD ROM to ensure that the basic functions operate normally on all systems.Fans usually spend a lot of time manually adjusting memory timing to improve speed.
The Enhanced Performance Profile is an SPD extension that is created byNvidiaandCorsairDevelopment, which includes makingDDR2 SDRAMAdditional information for higher performance operation, such as power supply voltage and command timing information not included in JEDEC SPD specification.EPP information is stored in the same EEPROM, but the bytes are 99-127, which belongs to the unused area in the DDR2 SPD standard.
These parameters are designed fornForce 5、nForce 6andnForce 7On chipsetMemory controllerDesign.Nvidia encouragesBIOSHigh endMainboard chipsetSupport EPP.This function is designed to provide "one buttonOverfrequency”For better performance with minimal effort.
Nvidia provides the name "SLI Ready Memory" for EPP memory with certified performance and stability.The term "SLI Ready memory" causes some confusion because it is similar toNVIDIA SLIirrelevant.Users can use a single video card (even non Nvidia card) with EPP/SLI memory, or run multi card SLI video configuration without EPP/SLI memory.
Its extended version EPP 2.0 supportsDDR3 memory。[1]
Extreme Memory Profile（XMP）
Similarly,IntelbyDDR3 SDRAMDIMMs have developed a JEDEC SPD extension.It uses JEDEC unallocated bytes 176-255 to encode higher performance memory timing.Also known in Chinese as "Extended Memory Configuration", the header contains the following data.The most important one is the "medium time base" value MTB, which is a reasonable nanosecond (the commonly used values are 1/8, 1/12 and 1/16 nanoseconds).Many subsequent timing values are expressed in integer MTB units.
The header also includes the number of DIMMs for each memory channel that the configuration file is intended to support;More DIMMs may not work properly.
AMD has also developed an SPD extension set named AMP, which has the same function as XMP.[1]
Vendor specified memory
A common abuse is to write information to certain memory areas to bind specific vendor memory modules to specific systems.KnownFujitsu Technology Solutions Yes.Adding different memory modules to the system usually results in rejection of operation or other countermeasures (for example, pressing F1 every time you start).
This is the output of a 512 MB memory module of Micron Technology. Its brand isFujitsu Siemens, note the "FSC" string.The system BIOS rejects memory modules without this information from offset 128h.[1]
Reading and writing SPD information
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The memory module manufacturer will write the SPD information to theEEPROM。The motherboard BIOS reads the SPD information to configureMemory controller。In most (but not all)Mainboard chipsetThere are several programs that can read and modify SPD information.
dmidecodeThe program can decode information about memory (and others)Linux、FreeBSD、NetBSD、OpenBSD、BeOS、CygwinandSolarisRun on.Dmidecode does not directly access SPD information;It reports BIOS data about memory.This information may be limited or incorrect.
stayLinuxOn the system,User spaceThe program decode dimms can decode and print any memory information with SPD information in the computer with i2c tools.It needs to be supported in the kernelSMBusController, EEPROM core driver, and SPD EEPROM connected to SMBus.On older Linux distributions, decode dimms. pl was used aslm_sensorsA portion of is available.
OpenBSD has drivers since version 4.3spdmem(4)To provide information about the memory module.The driver is migrated from NetBSD (available since version 5.0).
CorebootRead and use SPD information to initialize allMemory controllerThe timing, size, and other attributes of.
WindowsUse on such asHWiNFO32、CPU-ZorSpeccyThe software can read and display the DRAM module information in SPD.
Using EEPROM programmer hardware and software to directly access EEPROM memory, you can directly read and write SPD information without caring about chipsets.
For old laptops, a less common use is the general SMBus reader, because the BIOS can disable the internal EEPROM on the module after reading, so the bus can basically be used.The method used is to pull A0 and A1 wires down so thatInternal memoryTurn off to allow external devices to access the SMBus.After this operation, the customizedLinux versionOr DOS applications can access external devices.A common purpose of doing this is toMemory chipRecover data in, and modify the general panel to be dedicated to notebook computers.[1]
On old equipment
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Some older equipment must be equipped withparallelPresence detection (often referred to as simple presence detection, or abbreviated PD)SIMM。Some of these devices use non-standard PD codes, especially such asIBMComputerHPLaserJet, and some other printers.[1]
