Quartus

design environment

Quartus II Design is the most advanced and complex, used for system-on-a- programmable -chip ( SOPC ）Design environment for. Quartus II design provides perfect timing closure and LogicLock ™ Block based Design process 。 Quartus II design is the only programmable logic device with the basic characteristics of timing closure and block based design flow（ PLD ）Software. Quartus II design software improves performance, improves functionality, solves potential design delays, and takes the lead in providing FPGA Unified development with mask programmed devices Workflow 。

Chinese name: Quartus
Nature: Design environment.

Improvements: Performance, improved functionality
Related: The fourth generation PLD development platform

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one brief introduction
two Performance characteristics

brief introduction

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Quartus

Altera Quartus II as a Programmable Logic Because of its powerful Design capability And intuitive and easy to use interface, more and more digital system Welcome of designers. The latest version available for download is v18.0.

Altera Quartus II (3.0 and higher) design software is the only one available in the industry FPGA Unified with fixed function HardCopy device Design process Of design tool 。 Engineers use the same low-cost tool to implement the functional verification and Prototype design You can also design HardCopy Stratix devices for batch products. System designers can use Quartus II Software evaluation The performance and power consumption of HardCopy Stratix devices are maximized accordingly throughput Design.

Altera Quartus II programmable logic software belongs to the fourth generation PLD Development platform 。 The platform supports the design requirements of a workgroup environment, including supporting Internet based collaborative design. Quartus platform and Cadence 、 ExemplarLogic、 MentorGraphics、 Synopsys And Synplicity and other EDA suppliers development tool Compatible. Improved the LogicLock module design function of the software, added the FastFit compilation option, and promoted Network Editing Performance, and improved debugging ability.

Performance characteristics

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Support products such as MAX7000/MAX3000

Version 2.0 Quartus II design software supports Altera APEX 20KE, APEX 20KC， APEX II， ARM Of Excalibur The embedded processor scheme supports MAX3000A in addition to Mercury, FLEX10KE and ACEX1K, MAX7000 Series product term device. MAX3000A and MAX7000 designers can use QuartusII All the powerful functions that only exist in the design software.

The software volume is reduced, running speed accelerate

The installation software of Quartus II2.0 is 290M, and the full installation is 700M. If the installation is customized, do not select Excalibur If the processor is embedded, the installation space is 460M, which is less than half of the space requirement of Quartus II 1.1, but it can support the development of all ALTERA chips. At the same time, software loading, compilation and simulation Speed ratio Version 1.1 is greatly accelerated.

LogicLock design process improves performance by 15%

QuartusII2.0 design software improves the performance by an average of 15% by enhancing the hierarchical LogicLock module level design method. The LogicLock design process puts the placement of the entire module under the control of the designer. If necessary, an assistant can be used Plane layout 。 LogicLock design Process operation The designer individually optimizes and locks the performance of each module SOPC The performance of the whole system is also maintained during the design and construction process. Version 2.0 Quartus II design software integrates the new LogicLock design process algorithm into the future Altera In the device, the algorithm makes full use of the advantages of module level design.

Shorten with quick fit option Compilation time

Quartus II 2.0 has added a new fast adaptation compilation option. If you select this option, it will be 50% shorter than the default setting Compilation time 。 The quick adaptation function retains the best performance settings and speeds up the compilation process. In this way, the layout adaptation algorithm has fewer iterations, faster compilation speed, and minimal impact on design performance.

New features are reduced System level verification

The version 2.0 Quartus II design software introduces new functions to speed up the verification process, which is usually the longest stage in the SOPC design process. In the initial compilation time, the new SignalProbe technology allows the user to keep the original wiring, time limit and Design documents At the same time Internal nodes Lead to unused pins for analysis. SignalProbe technology has completed the embedding of existing SignalTap logic analysis Function of. Moreover, designers can use the HDL Test templates quickly develop HDL simulation vectors.

Version 2.0 of the Quartus II design software can also automatically simulator Wave file Create a complete HDL in Test platform 。

Version 2.0 of the Quartus II design software also supports high-speed I/O design and generates dedicated I/O buffer Information specification（ IBIS ）The model is imported into the common EDA signal integration tool. IBIS model According to the I/O Standard settings to simplify the analysis of third-party tools.

Version 5.0 or above support Dual core CPU embedding.

Altera will shorten its compilation speed every time it releases a new version. Because its compilation speed is really slow.

The kernel means Soft nucleus (Users can customize corresponding functions according to their own needs) NIOS II realization.

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