It's cancelleda main boardAnd memoryStorage cycleThe time interval between two clock pulse cycles is shortened greatlyAccess time, makeAccess speedIncrease by 30% to 60ns.EDO memory is mainly used for 72 line SIMMMemory module, and the adoption of EDOMemory chipPCI display card.This kind of memory is popular in 486 and early Pentiumcomputer systemIt has 72 lines and 168 lines. It uses 5V working voltage and 32 bit bus width. Two or four lines must be used in pairs. It can be used on Intel 430FX/430VX or even 430TX chipset motherboards.At present, it has also been eliminated and can only be seen on some master planes.
working principle
Announce
edit
[1]
There is a big difference between EDO DRAM and the older FPM DRAM in the way that the next data is read only after the data is read.EDO DRAM can gate the next column address while outputting data. We still use the following EDO reading sequence diagram to understand the process of EDO DRAM reading data:
EDO DRAM
1. RAS enters the pre charging state after the last read operation. When receiving a request to read data, the line address is first transmitted to the address pin through the address bus. During this period, CAS is still in the pre charging state.2. When the/RAS pin is activated, the column address starts to select the line address through the line address strobe circuit and the line address decoder. At the same time, the tRAC cycle starts. Because the read operation/WE pin has not been activated, the memory knows that it is reading rather than writing.
3. While CAS is still precharging, the column address is sent to the column address strobe circuit to select the appropriate address. When/CAS is activated, the tCAC cycle starts. When tCAC ends, the data to be read will be transmitted to the data bus through the data pin.
4. From the beginning of outputting the first group of data, we can realize the difference between EDO and FPM: before the end of the tCAC cycle, CAS deactivates and starts to pre charge, the second group of column address transmission and gating also starts immediately, and before the first data is outputted, the tCAC cycle of the next group of data starts - obviously this further saves time.Just before the second group of data is output, CAS is deactivated again to prepare for the third group of data transmission column address
