DMA (Direct Memory Access) is a function provided by some computer bus architectures, which enables data to be sent directly from additional devices (such as disk drives) toComputer motherboardIn memory.
Usually a memory section is specified for direct memory access.In the ISA bus standard, up to 16 megabytes of memory can be used for DMA.EISA and microchannel architecture standards allow access to a full set of memory addresses (assuming they can be addressed with 32-bit).Peripheral device interconnection uses a bus master to complete direct memory access.
Another option for direct memory access is programmable I/O（PIO）Interface.In the program-controlled I/O interface, all data transmission between devices must pass through the processor.The new protocol of ATA/IDE interface isUltra DMAIt provides a burst data transmission rate of 33 megabytes per second.With Ultra DMA/33Hard driveAlso supportedPIO mode1. 3, 4 and Multiword DMA mode 2 (16.6 megabytes per second).[1]
principle
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The data transmission between peripheral devices and memory and between memory and memory usually adopts program interrupt mode, program query mode and DMA control mode.Both program interrupt mode and program query mode require the CPU to issue input/output (In/Out, I/O) instructions, and then wait for the I/O device to complete the operation before returning. During this period, the CPU needs to wait for the I/O device to complete the operation.When DMA transfers the data of memory and I/O devices, it does not need CPU to control the data transmission, and the high-speed data transmission between peripheral devices and memory as well as between memory and memory is completed directly through DMA controller (DMAC).[3]
DMA transmission principle
A complete DMA transfer includes four steps: DMA request, DMA response, DMA transfer and DMA end.The DMA transmission principle is shown in Figure 1. The I/O device in the figure is the source device, and the I/O device transfers data to the destination device (memory). The basic DMA transmission process is as follows: ① The CPU initializes the bus controller, formulates the working memory space, reads the register information in the DMAC, and understands the transmission status of the DMAC [1]; ②I/O device sends DMA request (DREQ) to DMAC, and DMAC sends bus hold signal (HOLD) to CPU after receiving this signal; ③The CPU sends the bus response signal hold acknowledgement (HLDA) after the end of the current bus cycle execution; ④ After the DMAC receives the bus authorization, it sends the DMA response signal DMA acknowledgement (DACK) to the I/O device, indicating that the I/O device is allowed to carry out DMA transmission; ⑤At the beginning of transmission, DMAC first reads data from the source address and stores it in the internal cache, and then writes the destination address to complete the transmission of bus data from the source address to the destination address [1]; ⑥After DMA transmission is completed, the DMAC sends an end signal to the CPU to release the bus so that the CPU can regain control of the bus.One DMA transmission only needs to execute one DMA cycle, which is equivalent to a bus read/write cycle, so it can meet the needs of high-speed peripheral data transmission.[3]
DMA is an important feature of all modern computers. It allows hardware devices with different speeds to communicate without relying on a large number of CPUinterruptLoad.Otherwise,a central processorYou need to copy each piece of data from the source toregisterAnd then write them back to the new place again.At this time, the central processing unit cannot be used for other work.
DMA transfer is often used to copy a memory area from one device to another.Whena central processorInitialize this transfer action. The transfer action itself is created byDMA controllerTo implement and complete.A typical example is to move a block of external memory to the faster memory inside the chip.Such operations do not delay the processor's work, so that it can be rescheduled to handle other work.DMA transmission is very important for high-performance embedded system algorithms and networks.For example, the ISADMA controller of a personal computer has 8 DMA channels, of which 7 channels can be used by the central processing unit of the computer.Each DMA channel has one16 bitAddress registerAnd a 16 bitCount register。To initialize data transmission, the device driver sets the address and count register of the DMA channel, as well as the direction of data transmission, and reads or writes.Then instruct the DMA hardware to start this transfer action.When the transmission ends, the device will notify the central processing unit by interrupt.
Scatter gather DMA allows data to be transferred to multiple memory areas in a single DMA process.It is equivalent to stringing multiple simple DMA requirements together.Similarly, the purpose of this is to alleviate the CPU's multiple output and input interrupts and data replication tasks.DRQ means DMA requirements;DACK means DMA confirmation.These symbols can generally be seen on the outline of computer system hardware with DMA function.They indicate that between the CPU andDMA controllerElectronic signal transmission line between.[1]
Cache consistency problem
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DMA will causecacheConsistency issues.Imagine the CPU with cache and external memory,The operation of DMA is to access the external memory. When the central processor accesses an address of the external memory, it temporarily writes the new value to the cache, but does not update the data in the external memory. If DMA occurs before the data in the cache has been updated to the external memory, the DMA process will read the data that has not been updated.
Similarly, if an external device writes a new value to the external memory, the CPU will access the data that has not been updated when accessing the cache.
These problems can be solved in two ways:
one
Cache coherence system: It is completed by hardware method. When an external device writes to the memory, it uses a signal to notify the cache controller that the value of a memory address has expired or that data should be updated.
two
Non coherent system: completed by software,operating systemWhen the cache read must be confirmed, the DMA program has started or DMA is prohibited.
The second method will cause the system burden of DMA.[2]
DMA engine
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In addition to hardware interaction, DMA can also reduce the burden of expensive memory consumption.For example, large copy operations or scatter gather operations, from the CPU to the dedicated DMA engine.IntelThe high-end server of includes this engine, which is calledI/O acceleration technology（IOAT）。[2]
RDMA
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In the field of computer computing,Remote Direct Memory Access(English:remote direct memory access，RDMA）Is a kind ofDirect memory accessTechnology, which takes data directly from a computer'sMemoryTransfer to another computer without both partiesoperating systemThe intervention of.This allows high throughput, lowdelayNetwork communication, especially suitable for large-scale parallelComputer clusterUsed in.
RDMA supportZero replicationNetwork transmission by makingnetwork adapterTransfer data directly between application memory, no longer need to copy data between application memory and operating system buffer.This transmission does not requirea central processor、CPU cacheOr context exchange, and the transmission can be parallel with other system operations.When an application executes an RDMA read or write request, the application data is directly transmitted to the network, thereby reducing latency and enabling fast message transmission.
However, this strategy also shows that the target node will not receive the notification of request completion (one-way communication) and other related problems.[2]
