DDR3 SDRAM(Double Data Rate Three Synchronous Dynamic Random Access Memory)Computer memorySpecifications.It belongs toSDRAMFamilialstorageProduct, providingDDR2 SDRAMHigher operating performance and lower voltage are the successors of DDR2 SDRAM (quadruple data rate synchronous dynamic random access memory) (increased to eightfold).
Chinese name
Third generation double data rate synchronous dynamic random access memory
DDR2 SDRAMThere are 4 Bank and 8 Bank designs in order to meet the demand for high-capacity chips in the future.DDR3 is likely to start with 2Gb capacity, so there will be 8 logical banks at the beginning. In addition, it is also ready for 16 logical banks in the future.[1]
encapsulation
Packages DDR3 has some new functions, so the pins will be increased. The 8bit chip uses 78 ballsFBGA package16bit chip is packaged with 96 ball FBGA, while DDR2 has 60/68/84 ball FBGA package.And the DDR3 must be green sealed and cannot contain anyHazardous substances。[1]
Burst length (BL, Burst Length) Since the prefetch of DDR3 is 8 bitsBurst transmissionThe cycle (BL, Burst Length) is also fixed to 8. For DDR2 and early DDR architecture systems, BL=4 is also commonly used. For this reason, DDR3 adds a 4-bit Burst Chop mode, that is, a BL=4 read operation plus a BL=4 write operation compose a BL=8 data burst transmission. At that time, A12 can be usedAddress lineTo control this burst mode.It should also be noted that any burst interrupt operation will be prohibited in the DDR3 memory and will not be supported. Instead, more flexible bursts will be usedTransmission control(e.g. 4bit sequential burst).[1]
Addressing sequence
Addressing timing is just like the number of delay cycles increases after DDR2 is transformed from DDR. The CL cycle of DDR3 will also be higher than that of DDR2.The CL range of DDR2 is generally between 2 and 5, while DDR3 is between 5 and 11, and the design of additional delay (AL) has also changed.For DDR2, the range of AL is 0 to 4, while for DDR3, AL has three options: 0, CL-1, and CL-2.In addition, DDR3 also adds a new timing parameter - write delay (CWD), which will be based on the specificworking frequency It depends.From the perspective of environmental protection, reducing power consumption has made a real contribution to the industry. The annual power consumption of PCs around the world is quite amazing. Even if each PC is reduced by 1W, its power saving is very considerable.[1]
Reduce power consumption
When DDR3 memory reaches high bandwidth, its power consumption can be reducedworking voltage fromDDR21.8V drops to 1.5V, and relevant data predicts that DDR3 will save 30% of power consumption than current DDR2. Of courseCalorific valueWe don't need to worry.Make a balance between bandwidth and power consumption. Compared with existing DDR2-800 products, the power consumption ratios of DDR3-800, 1066 and 1333 are 0.72X, 0.83X and 0.95X, respectivelyMemory bandwidthThe power consumption performance is also better than that of the previous generation.[1]
Main differences
Announce
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Specifications
Specifications are shown in Figure 1[1]
Figure 1 DDR2 Specification
Figure 1 DDR3 Specification
New Features
New function - Reset
Reset YesDDR3An important function has been added, and a pin has been specially prepared for this purpose.DRAMThe industry has long requested to add this function, and now it is finally implemented on DDR3.This pin will simplify the initialization of DDR3.When the Reset command is valid, DDR3 memory will stop all operations and switch to the least active state to save power.During Reset, most of the internal functions of DDR3 memory will be disabled, so the data receiver and transmitter will be disabled.All internal program devices will be reset,DLL(DelayPhase-locked loop）AndClock circuitWill stop working and ignoredata busAny movement on.In this way, DDR3 will achieve the goal of saving the most power.[1]
New function - ZQ calibration
ZQ is also a new pin, which is connected with a 240 ohm low tolerance reference resistor.This pin is automatically verified through a command set and ODCE (On Die Calibration Engine)data outputDriverOn resistanceAnd ODT.When the system sends this command, the correspondingClock cycle(512 clock cycles are used after power on and initialization, 256 clock cycles are used after exiting the self refresh operation, and 64 clock cycles are used in other cases) Recalibrate the on resistance and ODT resistance.[1]
The reference voltage signal VREF, which is very important for the memory system, will be divided into two signals in the DDR3 system.One is VREFCA for commands and address signals, and the other is VREFCA fordata busVREFDQ, which will effectively improve the signal-to-noise level of the system data bus.[1]
SRT
Auto refresh based on temperature (SRT)To ensure that the saved data is not lost, DRAM must be refreshed regularly, and DDR3 is no exception.However, in order to maximize power savings, DDR3 uses a new automatic self refresh design (ASR,Automatic Self-Refresh）。When ASR is started, the refresh frequency will be controlled by a temperature sensor built into the DRAM chip, becauserefresh frequencyIf high,Power extinctionThe higher the temperature, the higher the temperature.andTemperature sensorUnder the condition of ensuring no data loss, try to reduce the refresh frequency andworking temperature 。However, the ASR of DDR3 is an optional design. It is not likely that DDR3 memory in the market supports this function. Therefore, an additional function is the self refresh temperature range (SRT,Self-Refresh Temperature）。Pass ModeregisterTwo temperature ranges can be selected, one is the general temperature range (such as 0 ℃ to 85 ℃), and the other is the extended temperature range, such as the maximum temperature of 95 ℃.For the two temperature ranges set internally by DRAM, DRAM will refresh at a constant frequency and current.[1]
RASR
Local self refresh (RASR)This is an option of DDR3. With this function, the DDR3 memory chip can refresh only part of the logical Bank, rather than all of it, so as to minimize the self refreshPower consumption。This is similar to the design of Mobile DRAM.[1]
Point to pointConnection (P2P, Point to Point) This is to improvesystem performance Important changes have also been made toDDR2A key difference in the system.In a DDR3 system, oneMemory controllerOnly one memory channel will be contacted, and this memory channel can only have one socket.So the memory controller and DDR3Memory moduleIt is a point-to-point (P2P, Point to Point) relationship (module of a single physical bank), or a point-to-point (P22P, Point to two Point) relationship (module of a dual physical bank), which greatly reduces the load of address/command/control and data bus.In terms of memory module, it is similar to the type of DDR2, but there are also standardsDIMM(desktop PC)SO-DIMM/Micro-DIMM（Notebook computer）、FB-DIMM2 (servers), of which the second generation FB-DIMM will use AMB2 (advanced memoryBuffer）。However, the standard formulation of DDR3 memory module has just begun, and the pin design has not been finalized.[1]
