The housing for installing semiconductor integrated circuit chip plays the role of placing, fixing, sealing, protecting the chip and enhancing the electrothermal performance. It is also a bridge between the internal world of the chip and the external circuit - the contacts on the chip are connected to the pins of the packaging housing with wires, which are connected to other devices through the wires on the printed board.Therefore, packaging plays an important role in CPU and other LSI integrated circuits
Chinese name
Chip packaging
Object
CPU and other LSI integrated circuits
Category
Computer circuit
Role
Placement, fixation, sealing and protection of chips
Since Intel Corporation designed and manufactured 4-bit microprocessor chips in 1971, CPU has developed from Intel 4004, 80286, 80386, 80486 to Pentium, P Ⅱ, P Ⅲ, P4, and from 4-bit, 8-bit, 16 bit, 32-bit to 64 bit in more than 20 years;The main frequency has developed from MHz to today's GHz;The number of transistors integrated in CPU chips has jumped from more than 2000 to more than 10 million;The scale of semiconductor manufacturing technology is from SSI, MSI, LSI, VLSI (ultra large scale integrated circuit) to ULSI.The number of encapsulated input/output (I/O) pins has increased from dozens to hundreds, or even 2000.All this is really an earth shaking change.
Common integrated circuit
You are already familiar with the CPU, 286, 386, 486, Pentium, P Ⅱ, Celeron, K6, K6-2, Athlon... I believe you can list a long list as you know it.But when it comes to the packaging of CPU and other large-scale integrated circuits, not many people know about it.The so-called packaging refers to the housing used to install semiconductor integrated circuit chips. It not only plays the role of placing, fixing, sealing, protecting the chips and enhancing thermal conductivity, but also serves as a bridge between the internal world of the chip and the external circuit -- the contacts on the chip are connected to the pins of the packaging housing with wires,These pins are connected with other devices through wires on the printed circuit board.Therefore, packaging plays an important role in CPU and other LSI (Large Scala Integration~on) integrated circuits. The emergence of a new generation of CPU is often accompanied by the use of new packaging forms.The chip packaging technology has gone through several generations of changes. From DIP, QFP, PGA, BGA, CSP to MCM, the technical indicators are more advanced from generation to generation, including the ratio of chip area to packaging area getting closer to 1, the application frequency getting higher and higher, and the temperature resistance getting better and better.The number of pins increases, the spacing between pins decreases, the weight decreases, the reliability improves, and the use is more convenient.[1]
Common types
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DIP dual in-line
DIP (Dual Inline pin Package) refers to theIntegrated circuitChips, the vast majority of small and medium-sized integrated circuits (ICs) adopt this packaging form, and the number of pins is generally not more than 100.CPU chip packaged with DIP has two rows of pins, which need to be inserted into the chip socket with DIP structure.Of course, it can also be directly inserted into the circuit board with the same number of solder holes and geometric arrangement for soldering.The DIP packaged chip shall be inserted and pulled out from the chip socket with special care to avoid damage to the pins.
characteristic:
1. It is suitable for punching and welding on PCB (printed circuit board) and easy to operate.
2. The ratio between package area and chip area is large, so the volume is also large.
8088 of Intel series CPU adopts this packaging form, cache and earlyMemory chipThis is also the packaging form.
Component encapsulated
PQFP (Plastic Quad Flat Package) packages have very small distances between chip pins and very thin pins. Generally, large-scale or ultra large integrated circuits adopt this packaging form, and the number of pins is generally more than 100.The chip packaged in this form must be soldered to the motherboard using SMD (Surface Mount Device Technology).The chip installed by SMD does not need to punch holes on the main board. Generally, there are designed solder joints of corresponding pins on the surface of the main board.Align the pins of the chip with the corresponding solder joints to realize the welding with the motherboard.The chip soldered in this way is difficult to remove without special tools.
PFP (Plastic Flat Package) chips are basically the same as PQFP chips.The only difference is that PQFP is generally square, while PFP can be either square or rectangular.
characteristic:
1. Applicable to SMD surface mounting technologyPCB circuit boardInstall wiring on the.
2. Suitable for high-frequency use. 3Convenient operation and high reliability.
4. The ratio between chip area and package area is small.
The 80286, 80386 and some 486 motherboards in Intel series CPUs adopt this packaging form.
PGA pin net format
PGA (Pin Grid Array Package) chip packaging has multiple square array pins inside and outside the chip, and each square array pin is arranged at a certain distance along the periphery of the chip.According to the number of pins, it can form 2-5 circles.During installation, insert the chip into the special PGA socket.In order to make it easier to install and disassemble the CPU, a CPU socket called ZIF has emerged from the 486 chip, which is specially used to meet the requirements of PGA packaged CPUs on installation and disassembly.
ZIF (Zero Insertion Force Socket) refers to the socket with zero insertion force.By gently lifting the wrench on the socket, the CPU can be easily and easily inserted into the socket.Then press the wrench back to the original place, and use the extrusion force generated by the special structure of the socket itself to firmly contact the CPU pin with the socket. There is absolutely no problem of poor contact.To remove the CPU chip, just gently lift the wrench of the socket, the pressure is relieved, and the CPU chip can be easily taken out.
characteristic:
1. It is more convenient and reliable to plug and unplug.
2. It can adapt to higher frequency.
Among Intel series CPUs, 80486, Pentium and Pentium Pro all adopt this packaging form.
BGA ball grid array
With the development of integrated circuit technology, the packaging requirements for integrated circuits are more stringent.that is becausePackaging technologyWith regard to the functionality of the product, when the frequency of the IC exceeds 100MHz, the traditional packaging method may produce the so-called "CrossTalk" phenomenon, and when the number of pins of the IC is greater than 208 Pin, the traditional packaging method has its difficulties.Therefore, in addition to using PQFP packaging, most of today's high pin chips (such as graphics chips and chipsets) use BGA (Ball Grid Array Package) packaging technology instead.As soon as BGA appeared, it became the best choice for high-density, high-performance, multi pin packaging such as CPU, South/North Bridge chip on the motherboard.
BGA packaging technology can be divided into five categories
1. PBGA (Plastic BGA) substrate: generally, it is a multilayer board composed of 2-4 layers of organic materials.Among Intel series CPUs, Pentium II, III and IV processors all adopt this packaging form.
2. CBGA (CeramicBGA) substrate: ceramic substrate. FlipChip (FC) is usually used for the electrical connection between chips and substrates.Among Intel series CPUs, Pentium I, II, and Pentium Pro processors have all used this packaging form.
3. FCBGA (FilpChipBGA) substrate: hard multilayer substrate.
4. TBGA (TapeBGA) base plate: the base plate is a 1-2 layer PCB circuit board with ribbon soft texture.
5. CDPBGA (Carity Down PBGA) substrate: refers to the chip area (also called cavity area) with square depression in the center of the package.
characteristic:
1. Although the number of I/O pins has increased, the distance between pins is far greater than that of QFP packaging, which improves the yield.
2. Although the power consumption of BGA increases, it can improve the electrothermal performance due to the controllable collapse chip welding method.
3. The signal transmission delay is small, and the adaptive frequency is greatly improved.
4. Coplanar welding can be used for assembly, which greatly improves the reliability.
After more than ten years of development, BGA packaging has entered the practical stage.In 1987, * * * Citizen began to develop the plastic ball grid array packaging chip (BGA).Later, Motorola, Compaq and other companies joined in the development of BGA.In 1993, Motorola took the lead in applying BGA to mobile phones.In the same year, Compaq also applied it to workstations and PCs.Until five or six years ago, Intel began to use BGA in computer CPUs (i.e. Pentium II, Pentium III, Pentium IV, etc.), as well as chipsets (such as i850), which played a role in promoting the expansion of BGA application fields.BGA has become extremely popularIC packagingThe global market size of technology was 1.2 billion in 2000. It is estimated that the market demand in 2005 will increase by more than 70% compared with 2000.
CSP chip size
With the global demand for personalized and lightweight electronic products, packaging technology has advanced to CSP (Chip Size Package).It reduces the size of the chip package, so that the size of the bare chip is as large as the package size.That is, the side length of the packaged IC size is not more than 1.2 times of the chip, and the IC area is only 1.4 times larger than the grain (Die).
CSP packaging can be divided into four categories
1. Lead Frame Type (traditional wire frame form), representative manufacturers include Fujitsu, Hitachi, RohmGoldstar (Goldstar) and so on.
2. Rigid Interposer Type, representative manufacturers include Motorola, Sony, Toshiba, Panasonic, etc.
3. Flexible Interposer Type, the most famous of which is Tessera's microBGA, and CTS's sim BGA also uses the same principle.Other representative manufacturers include General Electric (GE) and NEC.
4. Wafer Level Package: Different from the traditional single chip packaging method, WLCSP is to cut the whole wafer into individual chips. It is called the future mainstream of packaging technology. The manufacturers that have been invested in research and development include FCT, Aptos, Casio, EPIC, Fujitsu, Mitsubishi Electronics, etc.
characteristic:
1. It meets the increasing needs of chip I/O pins.
2. The ratio between chip area and package area is very small.
3. Greatly shorten the delay time.
CSP packaging is applicable to IC with few pins, such asMemory moduleAnd portable electronic products.In the future, it will be widely used in information appliances (IA), digital television (DTV), e-bookswireless networkWLAN/GigabitEthemet, ADSL/mobile phone chip, Bluetooth and other emerging products.
MCM multi chip modular
In order to solve the problems of low integration and incomplete functions of a single chip, multiple chips with high integration, high performance and high reliability are used on a high-density multi-layer interconnection substrate to form a variety of electronic module systems with SMD technology, which leads to the emergence of MCM (Multi Chip Module) multi chip module system.
characteristic:
1. The packaging delay time is reduced, which is easy to realize high-speed module.
2. Reduce the package size and weight of the whole machine/module.
3. The system reliability is greatly improved.[2]
classification method
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Packaging materials
Plastics, ceramics, glass, metal, etc,
Packaging form
Ordinary dual in-line, ordinary single in-line, small dual flat, small quad flat, round metal, bulky thick film circuits, etc.
Package volume
The largest is thick film circuit, followed by dual in-line, single in-line, metal package, dual row flat, quad row flat.
Pin spacing
Ordinary standard plastic package, double row and single row in-line type are generally 2.54 ± 0.25 mm, followed by 2mm (mostly seen in single row in-line type), 1.778 ± 0.25 mm (mostly seen in shrink type double row in-line type), 1.5 ± 0.25 mm, or 1.27 ± 0.25 mm (mostly seen in single row attached heat sink or single row V-type), 1.27 ± 0.25 mm (mostly seen in double row flatpack), 1 ± 0.15 mm (mostly seen in double row or four row flatpack)0.8 ± 0.05 ～ 0.15mm (mostly seen in four row flatpacks), 0.65 ± 0.03mm (mostly seen in four row flatpacks).
Pin width
Double in-line sealing rotorGenerally, there are 7.4~7.62mm, 10.16mm, 12.7mm, 15.24mm, etc.
Dual rank flatpack(including the length of the lead wire) is generally 6~6.5 ± mm, 7.6 mm, 10.5~10.65 mm, etc.
Quad Row Flatpack（The length × width above 40 pins generally includes 10 × 10mm (excluding the lead length), 13.6 × 13.6 ± 0.4mm (including the lead length), 20.6 × 20.6 ± 0.4mm (including the lead length), 8.45 × 8.45 ± 0.5mm (excluding the lead length), 14 × 14 ± 0.15mm (excluding the lead length), etc.[1]
Encapsulation steps
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The process of chip on board (COB) is first to cover the silicon wafer placement point on the substrate surface with thermal conductive epoxy resin (usually silver doped epoxy resin), then place the silicon wafer directly on the substrate surface, heat treat until the silicon wafer is firmly fixed on the substrate, and then directly establish electrical connection between the silicon wafer and the substrate by wire welding[3]。
There are two main forms of bare chip technology: COB technology and FlipChip technology.Chip on board packaging (COB): semiconductor chips are connected and pasted on the printed circuit board. The electrical connection between the chip and the substrate is realized by the lead suture method, and the electrical connection between the chip and the substrate is realized by the lead suture method, and is covered with resin to ensure reliability.Although COB is the simplest bare chip mounting technology, its package density is far lower than TAB and flip chip bonding technology[3]。
Main welding methods of COB
(1) Hot press welding
The metal wire and the welding area are pressure welded together by heating and pressure.The principle is to make the welding area (such as AI) plastic deformation and destroy the oxide layer on the pressure welding interface through heating and pressure, so as to generate attraction between atoms to achieve the purpose of "bonding". In addition, when the two metal interfaces are uneven, heating and pressure can make the upper and lower metals inlay each other.This technology is generally used for chip on glass COG[3]。
(2) Ultrasonic welding
Ultrasonic welding is to use the energy generated by the ultrasonic generator, through the transducer, under the induction of ultra-high frequency magnetic field, quickly expand and expand to produce elastic vibration, so that the cleat vibrates accordingly, and at the same time, apply a certain pressure on the cleat, so the cleat drives the AI wire to rapidly rub on the surface of the metallized layer (AI film) in the welded area under the combined action of these two forces,It makes the surface of AI wire and AI film produce plastic deformation, which also destroys the oxide layer at the interface of AI layer, making the two pure metal surfaces contact closely to achieve the bonding between atoms, thus forming welding.The main welding material is aluminum wire welding head, which is generally wedge-shaped[3]。
(3) Gold wire welding
Ball welding is the most representative welding technology in wire bonding, because the current semiconductor packaging diode and triode packaging uses AU wire ball welding.Moreover, it is easy and flexible to operate, with firm welding points (the welding strength of AU wire with diameter of 25UM is generally 0.07~0.09N/point), and has no directionality. The welding speed can be up to 15 points/second or more.Gold wire welding is also called thermal (pressure) (ultrasonic) welding. The main bonding material is gold (AU) wire. The welding head is spherical, so it is ball welding[3]。
COB packaging process
The first step: crystal expansion.The expander is used to uniformly expand the whole LED chip film provided by the manufacturer, so that the LED grains closely arranged on the film surface can be pulled apart for easy crystal pricking.Step 2: Adhesive backing.Place the expanded crystal ring on the surface of the back glue machine that has scraped the silver paste layer, and back the silver paste.Touch the silver paste.Suitable for bulk LED chips.Dot a proper amount of silver paste on the PCB printed circuit board with a glue dispenser.Step 3: put the crystal expanding ring with silver paste in the crystal stab rack, and the operator stabs the LED chip on the PCB printed circuit board with a stylus under the microscope.Step 4: Place the crystal punctured PCB printed circuit board in the thermal circulation oven and keep it at a constant temperature for a period of time, and take it out after the silver paste is cured (it cannot be placed for a long time, otherwise the LED chip coating will be yellowed, that is, oxidized, causing difficulties for bonding).If there is LED chip bonding, the above steps are required;If only the IC chip state rules, cancel the above steps.Step 5: Stick the chip.Use a glue dispenser to place an appropriate amount of red glue (or black glue) on the IC position of the PCB printed circuit board, and then use an anti-static device (vacuum pen or cartridge) to correctly place the IC blank on the red glue or black glue.Step 6: Drying.Put the bonded bare sheet into the thermal circulation oven and place it on the large flat heating plate at constant temperature for a period of time, or it can be naturally cured (for a long time).Step 7: Bangding (marking).The aluminum wire bonding machine is used to bridge the wafer (LED grain or IC chip) with the corresponding bonding pad aluminum wire on the PCB board, that is, the internal lead of COB is welded.Step 8: pre-test.Use special detection tools (COB has different equipment according to different purposes, and the simple one is high-precision regulated power supply) to detect COB boards, and rework unqualified boards.Step 9: Glue dispensing.The dispensing machine is used to place a proper amount of the prepared AB glue on the LED crystal, and the IC is sealed with black glue, and then the appearance is sealed according to the customer's requirements.Step 10: curing.Put the sealed PCB printed circuit board into the thermal circulation oven for constant temperature standing, and set different drying time according to requirements.Step 11: Post test.The packaged PCB printed circuit board is used for electrical performance test with special testing tools to distinguish between good and bad[3]。
Compared with other packaging technologies, COB technology is cheap (only about 1/3 of the same chip), space saving and mature.However, any new technology can not be perfect when it first appears. COB technology also has some shortcomings, such as the need for additional welding machines and packaging machines, sometimes the speed can not keep up, and PCB patches have more stringent environmental requirements and can not be maintained[3]。
Some chip on board (CoB) layouts can improve IC signal performance because they remove most or all of the packaging, that is, most or all of the parasitic devices.However, with these technologies, there may be some performance problems.In all these designs, the substrate may not be well connected to the VCC or ground due to the lead frame piece or BGA logo.Possible problems include coefficient of thermal expansion (CTE) problems and poor substrate connections[3]。
Development of Flip Chip Technology
More than 30 years ago, "flip chip" came out.At that time, it was named "C4", namely "controllable collapse chip interconnection" technology.The technology first uses copper, and then makes a high lead solder ball between the chip and the substrate.The connection between copper or high lead solder ball and substrate is realized by fusible solder.Soon after that, "flexible materials on caps (FOC)" applied to the automobile market appeared;Others further improved the C4 process by using Sn capping, that is, evaporation expansion fusible surface or E3 process.Although the C4 process is expensive to implement (including license fees and equipment costs), it still provides many performance and cost advantages for packaging technology.Different from the wire bonding process, flip chip can be completed in batches, so it is still cost-effective[3]。
As new packaging technologies and processes continue to emerge at an alarming rate, there is no major technical barrier to the completion of chip design with thousands of bumps. Small packaging technical engineers can easily complete various electrical, thermal, mechanical and mathematical simulations using new simulation software.In addition, the special tools designed by some world famous companies for internal use have been widely used.Therefore, designers can use these new tools and processes to maximize the design and shorten the time to market[3]。
No matter what attitude people have towards this, flip chip has begun a process and packaging technology revolution, and flip chip technology can still be in constant change after so many years of development due to the continuous emergence of new materials and new tools.In order to meet the ever-changing requirements of assembly process and chip design, new substrate technologies are being developed in the field of substrate technology, and simulation and design software are also constantly updated and upgraded.Therefore, how to balance the contradiction between the desire to design products with the latest technology and the appropriate style to launch products has become a major challenge that must be faced.Many designers and companies have to turn to flip chip technology due to the changing bandwidth of the Internet and some other factors listed below[3]。
Other factors include:
① Reduce signal inductance - 40Gbps (related to the design of base plate); ②Reduce power supply/grounding inductance; ③Improve signal integrity; ④The best thermal and electrical performance and the highest reliability; ⑤Reduce the number of encapsulated pins; ⑥The number of high convex points in the peripheral or entire array design that exceed the wire bonding capacity; ⑦Allowable when the pitch is close to 200 μ m;S chip shrinking (chips limited by solder joints); ⑧BOAC design is allowed, that is, bump design on the active circuit[3]。
