Control register

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Control register (CR0~CR3) is used to control and determine the operating mode of the processor and the characteristics of the currently executed task, as shown in Figure 4-3. CR0 contains the system control flag that controls the operating mode and status of the processor; CR1 remains unused; CR2 contains the Linear address ； CR3 contains page table of contents physical memory Base address, so this register is also called page directory base Address register PDBR（Page-Directory Base address Register）。

Chinese name: Control register

Field: assembly language

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three CR2 and CR3

Coprocessor control bit in CR0

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Four bits of CR0: extension type bit ET, task switching bit TS, simulation bit EM and mathematical presence bit MP are used to control 80x86 floating point (mathematical) Coprocessor Operation of. ET bit (flag) of CR0 is used to select and Coprocessor The protocol used for communication, that is, whether 80387 or 80287 is used in the system Coprocessor 。 TS, MP, and EM bits are used to determine whether a floating point instruction or WAIT instruction should generate a Device Not Available (DNA) exception. This exception can be used only for Floating point operation Save and restore tasks for Floating point register 。 For not used Floating point operation This can speed up the switching between them.

ET

Bit 4 of CR0 is the Extension Type flag. When this flag is 1, it indicates that there is 80387 in the system Coprocessor , and use the 32-bit coprocessor protocol. ET=0 indicates that 80287 coprocessor is used. If the emulation bit EM=1, this bit will be ignored. During the processor reset operation, the ET bit will be initialized to indicate the Coprocessor Type. If there is 80387 in the system, ET is set to 1; otherwise, if there is an 80287 or no coprocessor, ET is set to 0.

TS

Bit 3 of CR0 is the Task Switched flag. This flag is used to delay saving the coprocessor content during task switching until the new task starts to actually execute the coprocessor instructions. The processor sets this flag every time a task is switched, and tests this flag when executing coprocessor instructions.

If the TS flag is set and the EM flag of CR0 is 0, a device without exception will be generated before executing any coprocessor instruction. If the TS flag is set but the MP and EM flags of CR0 are not set, the exception free device will not be generated before executing the coprocessor instruction WAIT/FWAIT. If the EM flag is set, the TS flag pair Coprocessor The execution of instructions has no impact, as shown in Table 4-1.

Table 4-1 Effect of Different Combinations of Marks EM, MP and TS in CR0 on the Instruction Action of Coprocessor

Flag in CR0	Instruction type
EM	MP	TS	floating-point	WAIT/FWAIT
zero	zero	zero	implement	implement
zero	zero	one	The device does not have (DNA) abnormalities	implement
zero	one	zero	implement	implement
zero	one	one	DNA abnormality	DNA abnormality
one	zero	zero	DNA abnormality	implement
one	zero	one	DNA abnormality	implement
one	one	zero	DNA abnormality	implement
one	one	one	DNA abnormality	DNA abnormality

The processor does not automatically save when switching tasks Coprocessor Instead of setting the TS flag. This flag will make the processor perform new tasks Instruction flow Whenever you meet a Coprocessor There is no exception in the generated device when the command is given. The handler without exception can use the CLTS instruction to clear the TS flag and save it Coprocessor The context of. If the task has never been used Coprocessor , the corresponding coprocessor context does not need to be saved.

EM

Bit 2 of CR0 is the Emulation flag. When this bit is set, it indicates that the processor has no internal or external Coprocessor , the execution of coprocessor instructions will cause the device to be free from abnormalities; When cleared, it indicates that the system has a coprocessor. Setting this flag forces all floating-point instructions to use software to simulate.

MP

Bit 1 of CR0 is the monitor coprocessor (Monitor coProcessor or Math Present) flag. Used to control the interaction between WAIT/FWAIT instructions and TS flags. If MP=1, TS=1, executing the WAIT command will result in a device without exception; If MP=0, the TS flag will not affect the execution of WAIT.

Protection control bit in CR0

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PE

Bit 0 of CR0 is the Protection Enable flag. When this bit is set, the protection mode is turned on; When reset, it will enter the real address mode. This flag only enables segment level protection, but does not enable it paging Mechanism. To enable paging The PE and PG flags should be set.

PG

Bit 31 of CR0 is the Paging flag. When this bit is set, the paging mechanism is enabled; When resetting, the paging mechanism is disabled Linear address Equivalent to Physical address 。 The PE flag must be opened or simultaneously opened before opening this flag. That is, to enable the paging mechanism, the PE and PG flags must be set.

WP

For Intel 80486 or above CPUs, bit 16 of CR0 is Write Protect (Write Proctect) flag. When this flag is set, the processor will disable Super user Procedure (e.g Privilege level 0) to write to user level read-only pages; When this bit is reset, the reverse is true. This flag is helpful for UNIX like operating systems to implement Copy on Write technology when creating processes.

N

For Intel 80486 or above CPUs, bit 5 of CR0 is Coprocessor Numeric Error flag. When this flag is set, x87 is enabled Coprocessor Incorrect internal reporting mechanism; If this flag is reset, x87 coprocessor in PC form will be used Error Reporting Mechanism. When NE is reset and the IGNNE input pin of the CPU has a signal, the math coprocessor x87 error will be ignored. When NE is in the reset state and the IGNNE input pin of the CPU has no signal, the unmasked math coprocessor x87 error will cause the processor to generate an interrupt externally through the FERR pin and stop instruction execution immediately before executing the next wait form floating-point instruction or WAIT/FWAIT instruction. CPU FERR pin is used to simulate external Coprocessor The ERROR pin of 80387 is usually connected to the input request pin of the interrupt controller. NE flag, IGNNE pin and FERR pin are used to use external logic to realize external PC Error Reporting Mechanism.

Enable protection mode PE (Protected Enable) bit (bit 0) and enable paging PG (Paging) bit (bit 31) is used to control segmentation and paging mechanism respectively. PE is used to control the segmentation mechanism. If PE=1, the processor will work in the environment where the segmentation mechanism is enabled, that is, it will run in the protected mode. If PE=0, the processor turns off the segmentation mechanism and works like 8086 in the real address mode. PG for control paging Mechanism. If PG=1, it is enabled paging Mechanism. If PG=0, paging The mechanism is disabled Linear address Be directly treated as Physical address use.

If PE=0 and PG=0, the processor works in real address mode; If PG=0 and PE=1, the processor is not enabled paging Mechanism protection mode; If PG=1 and PE=0, the paging mechanism cannot be enabled when not in the protected mode, so the processor will generate a general protection exception, that is, this flag combination is invalid; If PG=1 and PE=1, the processor works in the protected mode with paging mechanism turned on.

Be careful when changing the PE and PG bits. Only when at least part of the code and data of the execution program have the same address in the linear address space and the physical address space, can we change the setting of the PG bit. At this time, the codes with the same address are paging And the non paged world. This part of code has the same address whether the paging mechanism is enabled or not. In addition, you must flush the page cache TLB before starting paging (PG=1).

After modifying the PE bit, the program must immediately use a jump instruction to refresh any instruction in different modes that the processor has acquired in the execution pipeline. Before setting the PE bit, the program must initialize several system segments and control registers. When the system is powered on, the processor is reset to PE=0 and PG=0 (i.e. real mode state) to allow the boot code to initialize these registers and data structures before enabling the segmentation and paging mechanism.

CR2 and CR3

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CR2 and CR3 are used for paging mechanisms. CR3 contains the physical address of the page directory table page, so CR3 is also called PDBR. Because the page of the page directory table is page aligned, only the upper 20 bits of this register are valid. The lower 12 bits are reserved for higher processors, so the lower 12 bits must be set to 0 when loading a new value into CR3.

Loading CR3 with the MOV instruction has the side effect of invalidating the page cache. To reduce the number of Bus cycle Number of pages visited in recent days and Page Table Will be stored in the processor's page cache device, which is called Translation Lookaside Buffer (TLB). Only when the TLB does not contain the required Page Table Item will be used Bus cycle Read page table entries from memory.

Even if the PG bit in CR0 is reset (PG=0), we can load CR3 first. To allow paging Mechanism. When switching tasks, the content of CR3 will also change. However, if the CR3 value of the new task is the same as that of the original task, the processor does not need to refresh the page cache. Share like this Page Table Tasks can be performed faster.

CR2 is used to report error information when a page exception occurs. When reporting page exceptions, the processor will Linear address Stored in CR2. So pages in the operating system exception handling The program can be determined by checking the contents of CR2 Linear address Which page in the space threw an exception.

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