On programmable chips (e.gsinglechip）, PLC, microcomputer, etcElectronic equipmentIn the process of running, the program will run off or jump, which can be sent to the hardware specific interface manually or automatically to restore the software operation to the specificProgram segmentRun, this process is the reset process;In this process, the signal sent to the specific interface of hardware by manual or automatic method is the reset signal.
Reset signals are mainly divided into two categories: synchronous reset signals and asynchronous reset signals.Synchronous reset signal refers to the signal generated by resetting the trigger when the effective edge of the clock arrives;The asynchronous reset signal does not depend on the clock signal. It is generated only when the system reset is valid.[1]
Synchronous reset signal
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advantage
1) Facilitate the analysis of static timing analysis tools
2) It can filter the burr with effective duration shorter than the clock cycle in the reset signal, and has high anti-interference
3) Facilitate the simulation of cycle based simulation tools
shortcoming
1) The effective duration of the reset signal must be greater than the clock cycle, otherwise the reset signal may not be collected
2) The reset behavior depends on the clock signal. If there is a problem with the clock signal, the reset behavior cannot be completed correctly
3) There are reset delay and combined logic delay
4) Since there are only asynchronous reset ports in the device library, if synchronous asynchronous reset is adopted, additional combination logic will be inserted during integration, which will take up more logic resources[1]
Asynchronous reset signal
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advantage
1) The identification method is simple and can be used for global reset
2) The design is relatively simple, does not require additional logical resources, and is easy to implement
3) Most devices in the device library have asynchronous reset ports, which can save resources
shortcoming
1) It is easy to have problems when the reset signal is released. If the reset is just released near the effective edge of the clock, it is easy to make the register output metastable
2) Asynchronous reset is easy to be triggered and affected by burrs, so the requirements for asynchronous reset source are high
3) It is difficult to conduct static timing analysis and simulation[1]
Reset signal importance
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With the development of integrated circuit design technology, the design scale of single chip circuit is becoming larger and larger, and the design complexity is correspondingly higher and higher.
At present, in integrated circuit design, especially in large-scale integrated circuit design represented by SoC (System on chip), synchronous timing design method is usually used.That is, all triggers in the chip work on the same clock signal, and the flip of trigger state also occurs at the same time.
The synchronous timing design method requires that the clock signal in the chip reaches each trigger in the chip at the same time.In fact, due to the different paths of the clock signal to each trigger, the delay of the clock signal on each trigger will be different.In order to ensure that the time when the clock edge reaches each trigger is the same, designers usually need to compensate for each path the clock goes through, that is, balance the clock tree.
Similarly, in the design of chip reset circuit, the delay of reset signal will also affect the digital logic of the circuit.As shown in Figure 1, the circuit between the reset signal input end (Rst) of three different circuit modules and the reset signal source (Reset) of the entire chip
Different connection paths may cause the reset signal delay as shown in Figure 2.When the reset signal is not synchronized, the output of each module has subsequent logic operations, which may cause the reset operation of module 2 and module 3 to still not be completed at the moment when the reset signal of module 1 disappears and starts to run, and the output is still in an uncertain state, thus leading to the bad result of chaotic system logic state.[2]
