Eight core processor There will be Wolfdale And Ridgefield. They both have two Dual core Of Single chip The desktop processor is expected to be released in 2008, and has 3 MB and 6 MB of L2 cache respectively. In addition, Perryville and Penryn , they are single core and dual core Core products The former has a 2 MB L2 cache, while the latter has 3 MB and 6 MB L2 cache. On the server, you can see the emergence of Hapertown. It will be a Xeon with 8 cores and have a shared 12 MB L2 cache. However, if you want to use 8-core processor products on the desktop platform, you will have to wait until 2008/2009, when Yorkfield will appear. It also has a 12 MB L2 cache.
In addition, the report also revealed the four core Bloomfield It will be launched at the same time as Yorkfield, but the number of L2 caches is unknown for the time being. Another Mobile platform It is unknown what kind of processor product Silverhorn will be. IBM [1] these two days stay microprocessor The Power5 processor shown on the has attracted a lot of attention due to its exaggerated appearance, which has caused quite a stir in the industry. Although we followed up the relevant information in time, its specific specifications are still a mystery. However, things finally turned around. With the official release of Power5 processor by IBM, we also got more relevant information. We have all seen that there are 8 cores of Power5, and the big guy in the hand is actually 4 CPU Composition should be called Multi chip module (MCM), the eight chips are four separate processors, each processor has two cores, and the area of each group of cores is relatively large, but they are similar to Intel's Itanium processor 450 of square millimetre In comparison, the core of Power5 is not large, only 389 square millimeters. In terms of manufacturing process, Power5 is manufactured by 0.13 μ m process and is based on 8-layer copper interconnection technology SOI technology. Such a large core, naturally transistor The number is not small. There are 276 million transistors in the area of 389 square millimeters, and there are about 5400 core pins, including 2313 data pins and 3057 power supply pins. These cores all have 8 execution unit , can be set in each Clock cycle 5 instructions and 4 octal floating-point data are processed in the Instruction Cache 32KB combined with 4-way Data cache They also share a super fast L2 Cache This L2 cache uses three independent buses, each 640KB, and the total L2 cache is 1.92MB. However, the data bandwidth of these cores is still unclear, but it is estimated that it will easily reach more than 200GB/s. We know that on processors like Power4 and Power5 L3 cache It's normal, but what's special about Power5 cache? Power5's three-level cache is built on MCM and runs at half speed. In this way, if a Power5 runs at 2GHz, its 36MB cache runs at 1GHz. With its 256 bit bus, its bandwidth can reach 32GB/s. This is very high for a cache outside the core. There is not much information about memory. It is estimated that 512 bit wide 8-channel will still be used DDR memory , support DDR333 、 DDR400 even to the extent that DDR2 -533, memory will provide 21GB/s bandwidth for each processor. In terms of the most interesting packaging, each of the four chips includes 8 real Processor unit , each processor unit is composed of 2 Logical processor So the whole MCM is 4 * 8 * 2=64 processors, that is, a 64 channel processing unit 。 On the other hand, each of the four L3 caches is 36MB, a total of 144MB. In terms of performance, there is no relevant test yet. It is estimated that it will increase by about 60% compared with the 1.7GHz Power4.
