With the rapid development of computer technology and microelectronics technology, embedded systems are used more and more widely.Energy saving is the upsurge of globalization. For example, many chips in computers used to be powered by 5V, but now they use 3.3V and 1.8V. The concept of green system is proposed.Many manufacturers attach great importance to the low power consumption of microcontrollers.Low power design of circuits and systems has always been an important factor for electronic engineering technicians to consider when designing.
At present, low power design is mainly considered from chip design and system design.With the rapid development of semiconductor technology and the increase of chip operating frequency, the power consumption of the chip increases rapidly, and the increase of power consumption will lead to the increase of chip heat and the decline of reliability.Therefore, power consumption has become an important consideration in the design of deep submicron integrated circuits.In order to make products more competitive, the requirements of industry for chip design have changed from simple pursuit of high performance and small area to comprehensive requirements for performance, area and power consumption.As the core component of digital system, microprocessor's low-power design is of great significance to reduce the power consumption of the whole system.
In the design of embedded systems, low power design is a problem that many designers must face. The reason is that embedded systems are widely used in portable and mobile products. These products do not always have sufficient power supply, and often rely on batteries to supply power,Therefore, designers consider reducing power consumption from every detail, so as to prolong the battery life as much as possible.In fact, it has become an increasingly urgent problem to consider low power design from a global perspective.
IC low power design
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tiny[1]For the low power design technology of processors, we must first understand the source of its power consumption.Among them, the clock unit (Clock) has the highest power consumption, because the clock unit has the clock load of the clock generator, clock driver, clock tree and clock control unit;Data path is second only to clock unit, and its power consumption mainly comes from operation unit, bus and register stack.In addition to the above two parts, there are memory, control and input/output (I/O). The power consumption of the storage unit is related to the capacity.
The power consumption of CMOS circuit mainly consists of three parts: dynamic power consumption caused by charging and discharging of circuit capacitor, power consumption caused by leakage current when junction reverse bias and power consumption caused by short-circuit current.Among them, dynamic power consumption is the most important, accounting for more than 90% of the total power consumption.
Common Low Power Design Techniques
Low power design is a complex and comprehensive subject.In terms of process, including power consumption modeling, evaluation and optimization;As far as design abstraction level is concerned, it includes all abstraction levels from system level to layout level.At the same time, power optimization is closely related to the optimization of system speed and area, which needs compromise.Common low-power design techniques are discussed below.
1) Dynamic voltage regulation
The dynamic power consumption is proportional to the square of the working voltage, and the power consumption will decrease at a quadratic rate with the decrease of the working voltage. Therefore, reducing the working voltage is a powerful measure to reduce power consumption.However, only reducing the operating voltage will result in increased propagation delay and longer execution time.However, the system load changes with time, so the microprocessor is not required to maintain high performance all the time.The main idea of dynamic voltage scaling (DVS) technology to reduce power consumption is to change the power management mode according to the chip working state, so as to reduce power consumption on the basis of ensuring performance.The operating voltage can be adjusted in different modes.In order to control the DVS accurately, the voltage dispatching module is needed to change the working voltage in real time. The voltage dispatching module predicts the working load of the circuit by analyzing the difference between the current and past system working conditions.
2) Gated clock and variable frequency clock
In microprocessors, a large part of power consumption comes from the clock.The clock is the only signal that is charged and discharged at all times, and in many cases causes unnecessary door overturning. Therefore, reducing the switching activity of the clock will have a great impact on reducing the power consumption of the whole system.The gating clock includes the gating logic module clock and the gating register clock.The clock of the gating logic module divides the clock network. If the system does not use some logic modules within the current clock cycle, the clock signal of these modules will be temporarily cut off, thus significantly reducing the switching power consumption.The clock control circuit is realized by "AND" gate.The principle of gated register clock is to turn off the register clock to reduce power consumption when the register holds data.However, the gated clock is prone to cause glitches, so the timing of the signal must be strictly limited and carefully verified.
Another common clock technology is variable frequency clock.It configures appropriate clock frequency according to system performance requirements to avoid unnecessary power consumption.In fact, the gated clock is an extreme case of the variable frequency clock (that is, there are only two values of zero and the highest frequency). Therefore, the variable frequency clock is more effective than the gated clock technology, but it requires the clock generation module PLL embedded in the system, which increases the design complexity.Last year Intel introduced the Montecito processor with advanced dynamic power control technology, which uses the frequency conversion clock system.A high-precision digital ammeter is embedded in the chip, and the total current is calculated by using the small voltage drop on the package;A 32-bit microprocessor is embedded to adjust the main frequency to achieve the purpose of 64 level dynamic power consumption adjustment, which greatly reduces the power consumption.
3) Parallel Architecture and Pipeline Technology
The principle of parallel architecture is to reduce power consumption by sacrificing area.A function module is copied into n (n ≥ 2) identical modules. These modules are selected for output through data selector after parallel calculation, and the parallel structure of two frequency division is adopted.
After parallel design, because there are multiple modules working at the same time, the throughput capacity is improved, and the speed of each module can be reduced to the original l/n.According to the linear relationship between the time delay and the working voltage, the working voltage can be reduced to the original l/n, the capacitance can be increased by n times, the working frequency can be reduced to the original l/n, and the power consumption can be reduced to the original 1/n2 according to formula (1).The key of parallel design is algorithm design. In general algorithms, the parallelism of parallel computing is often low, and algorithms with high parallelism are difficult to develop.For example, if the power consumption of the original module is P=a × CL × V2dd × f, and the frequency division structure is adopted, the whole capacitance load is 2.2CL, the working frequency is f/2, and the working voltage can be reduced to 0.6 V due to the addition of a module and data selector, then the power consumption is:
It can be seen that the dual frequency division parallel structure can maintain the original circuit performance while reducing the power consumption by 60%.
Pipeline technology is also a kind of parallelism in essence.A certain function module is divided into n stages for pipelining, each stage is completed by a sub module, and registers are inserted between sub modules, as shown in Figure 5.If the operating frequency is unchanged and the speed requirement for a module is only 1/n of the original, the operating voltage can be reduced to 1/n of the original, the capacitance changes little (the proportion of register area is very small), the power consumption can be reduced to 1/n2 of the original, the area is basically unchanged, but the complexity of control is increased.For example, if the power consumption of the original module is P=α × C1 × V2dd × f and pipeline technology is adopted, the whole capacitance load is 1.2CL due to the addition of registers, the operating frequency is unchanged, and the operating voltage drops to 0.6 V, then the power consumption is
：
It can be seen that pipeline technology can significantly reduce system power consumption.
The premise of reducing power consumption through pipeline technology and parallel structure is that the circuit operating voltage is variable.If the working voltage is fixed, these two methods can only improve the working speed of the circuit, and correspondingly increase the power consumption of the circuit.In the deep submicron process, the operating voltage is close to the threshold voltage. In order to make the operating voltage have enough room to decline, the wide value voltage should be reduced;However, with the decrease of threshold voltage, the sub threshold current will increase exponentially and the static power consumption will increase rapidly.Therefore, the space for voltage drop is limited.
4) Low power unit library
Design of low-power cell library is an important method to reduce power consumption, including adjusting cell size, improving circuit structure and layout design.Users can select circuits of different sizes according to the needs of load capacitance and circuit delay, which will lead to different power consumption. Therefore, units of different sizes can be designed according to needs.At the same time, low-power implementation structures such as triggers, latches, and data selectors are selected for commonly used units.
5) Low power state machine coding
The state machine coding has an important impact on the activity of the signal. By reasonably selecting the coding method of the state machine state and reducing the circuit flip during state switching, the power consumption of the state machine can be reduced.The principle is: for adjacent states with frequent switching, try to use adjacent coding.For example, Gray code has only one bit different value between any two consecutive codes. When designing the counter, Gray code replaces the binary code, and the number of counter changes is almost reduced by half, significantly reducing power consumption;When accessing the adjacent address space, the number of hops is significantly reduced, which effectively reduces the bus power consumption.
6) Low power design of Cache
As an important part of modern microprocessors, the power consumption of Cache accounts for 30%~60% of the power consumption of the whole chip. Therefore, the design of high-performance and low-power Cache structure plays an obvious role in reducing the power consumption of microprocessors.The key of cache low-power design is to reduce the failure rate and unnecessary operations.There are two methods commonly used to reduce cache power consumption: one is to design low-power memory based on memory structure, such as using CAM based cache structure;The other is to reduce power consumption by reducing the number of accesses to the cache.
The above is mainly to reduce power consumption from the perspective of hardware.In addition to the hardware method, the power consumption can also be significantly reduced through software optimization.For example, in the Crusoe processor, innovative technologies such as efficient VLIW, Code Morphing, LongRun power management, and RunCooler automatic temperature adjustment have been used to achieve good low-power results.
Low power design of embedded system
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In the design of embedded systems, low power design is a problem that many designers must face.
1) When energy-saving microprocessors are used in the same working state, power consumption increases nonlinearly due to different supply voltages.
We compare and select CPU performance and power consumption.Generally, it can be measured by the energy consumed every 1M instructions, that is, Watt/MIPS.However, this is only a reference indicator. In fact, the architecture of each CPU is very different, and the way to measure performance is also different. Therefore, we should further analyze some details.We divide the CPU power consumption into two parts: the core power consumption PCORE and the external interface controller power consumption PI/O. The total power is equal to the sum of the two, that is, P=PCORE+PI/O.For PCORE, the key lies in its power supply voltage and clock frequency;For PI/O, in addition to paying attention to the power consumption of each special I/O controller, you must also pay attention to the address and data bus width.
2) CMOS integrated circuit (CMOS integrated circuit), that is, complementary metal oxide semiconductor integrated circuit, shall be selected as far as possible. Its biggest advantage is micro power consumption (static power consumption is almost zero), and its second advantage is that the output logic level swing is large, so it has strong anti-interference ability, and its operating temperature range is wide,As a result, CMOS circuit has been bound up with low-power portable instruments since its appearance.
3) There is a functional relationship between the power consumption of battery low-voltage power supply system and the power supply voltage of the system.The higher the power supply voltage, the greater the power consumption of the system.At present, many low voltage power supply (less than 4.5V) single chip computers and their peripheral circuits have appeared, and the working voltage can be as low as 1.8V.It can work normally between 1.8V and 6V, and has no impact on the measurement accuracy.In the design and development, attention should be paid to that the power supply voltage of the single-chip microcomputer can be reduced from 6V to 1.8V, and the voltage can fluctuate in this range during the working period, but the domestic simulators can not meet this requirement, and generally work under 5V.At this time, there is a difference between the simulation and the real working state, so the low voltage test must be carried out after the design of the single-chip system to avoid problems in the actual application.
4) . Try to use the "high-speed and low-frequency" working mode. Almost all low-power monolithic microcomputer systems use CMOS devices. CMOS integrated circuits are determined by their own structure. Their static power consumption is almost zero. Only during the transition of logic state, the circuit has current flow.Therefore, its dynamic power consumption is proportional to its logic conversion frequency and logic state transition time of the circuit.Therefore, from the point of view of reducing power consumption, CMOS integrated circuits should convert quickly and work at low frequency.
5) . Make full use of the functions integrated on the microcontroller. The microcontroller has integrated many hardware into a chip. It is much more effective to use these functions than to expand the peripheral circuit in an extended way.First, the cost of monolithic is lower than that of using the expansion mode, and the performance is better.For example, it is difficult to reduce the driving voltage of peripheral devices to the level of the microcontroller chip, and the microcontroller can be reduced to 1.8V. If the peripheral circuit is reduced to 3V, I am afraid that a considerable number of chips will not work stably, while the hardware integrated in the microcontroller can have better voltage adaptability.
6) Select low power consumption and high efficiency peripheral devices and circuits When certain peripheral devices must be selected, try to select low power consumption, low voltage and high efficiency peripheral devices, such as LCD, EEPROM, etc., to reduce the overall power consumption of the system.In addition, low power consumption and high efficiency circuit forms shall be selected as far as possible.Low power consumption circuit takes low power consumption as the main technical index. It does not blindly pursue high speed and large driving ability, and takes meeting the requirements as the limit, so the working current of the circuit is relatively small.
development direction
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The improvement of people's requirements for the mobility of electronic products is limited by the development of battery capacity, and the design of low voltage and low power consumption has attracted more and more attention.The low voltage and low power design technology of analog circuits is limited by the working principle of circuits and the compatibility of digital circuits.The possible development directions in the future mainly include: First, further reduce the power supply voltage under the existing process.The measures taken can start with improving the circuit topology, so that the circuit can work by reducing the supply voltage when the threshold voltage is fixed.As early as 2000, Rout, S. realized the switching current unit operating at 1V power supply voltage under the common process.2、 Research new technology to make analog circuit and digital circuit more compatible, reduce leakage current of all devices, and provide signal to noise ratio for circuit processing.Document [17] pointed out that the use of a new dual gate MOS process and the use of the back gate to reduce the threshold voltage of the device can ensure that the designed adaptive two-stage operational amplifier circuit can still work normally when the power supply voltage is as low as 0.5V without sacrificing the circuit performance.3、 At present, the process characteristic linewidth and working voltage of digital circuits are still decreasing according to Moore's Law.Due to various reasons, the reduction speed of characteristic linewidth and working voltage of analog circuits is far lower than that of digital circuits.Therefore, the process compatibility of mixed design of digital analog circuits is a problem worthy of discussion.With the reduction of process size and power supply voltage, the design of analog integrated circuits will encounter many adjustments. It is very important to adopt accurate device models to carry out the design.Therefore, research on more accurate models of devices in deep submicron will be the direction of future efforts.
