Wafer Level Packaging (WLP) is a technology that completes packaging during semiconductor wafer manufacturing, aiming to improve the performance and reliability of integrated circuits (ICs), reduce package size, and reduce costs. This paper will comprehensively analyze the wafer level packaging structure.
Concept and advantages of wafer level packaging
Wafer level packaging technology is carried out in the final stage of wafer processing, that is, before the wafer is cut into a single chip. Compared with traditional packaging technology, WLP has many advantages: small size, light weight, short signal transmission distance, low cost and high production efficiency.
Classification of wafer level packaging
Wafer level packaging technology is mainly divided into two categories: wafer level chip size packaging (WLCSP) and integrated wafer level packaging (iWLP) ADUM1402CRWZ The chips are integrated on the same wafer.
Key Technologies of Wafer Level Packaging
● Thinning technology: wafers need to be thinned by back grinding technology before packaging to meet the requirements of thinness.
● Redistribution Layer (RDL) technology: form a new metal layer on the wafer surface to redistribute the layout of I/O solder joints to adapt to external connections.
● Solder ball stacking technology: form solder balls on RDL to realize electrical connection with the next level package or circuit board.
● Packaging substrate technology: It provides mechanical support and protection, and also serves as a bridge for electrical connection.
● Packaging material: must have good electrical performance, thermal stability and reliability.
Structure of wafer level package
A typical wafer level packaging structure includes the following parts:
1. Silicon chip: it is the main body of packaging, including complete integrated circuits.
2. Thin layer reduction: the back of silicon wafer processed by back grinding technology.
3. Redistribution Layer (RDL): Located on the surface of the silicon chip, it is used for the relocation of I/O points.
4. Protective layer: usually a layer of polymer material, used to protect RDL and chip surface.
5. Solder ball: usually made of tin lead or lead-free tin alloy, used for electrical connection.
6. Substrate: In some packaging structures, the substrate is used to provide additional support.
Process flow of wafer level packaging
The process flow of wafer level packaging mainly includes the following steps:
1. Wafer preparation: including cleaning and wafer thinning.
2. RDL formation: the redistribution layer is formed by photolithography, electroplating and other processes.
3. Solder ball stacking: electrical connection is formed through the solder ball stacking technology.
4. Package test: conduct electrical test on the packaged wafer.
5. Cutting and sorting: the wafer is cut into a single package chip and sorted.
Challenge and development of wafer level packaging
Wafer level packaging challenges include high-density I/O layout, thermal management, reliability assurance, and cost control. With the continuous progress of technology, wafer level packaging is developing towards higher I/O density, thinner package thickness, and better thermal and electrical performance.
conclusion
As an advanced packaging technology, wafer level packaging is of great significance to the development of microelectronics in the future. With the increasing demand for higher performance and smaller electronic products, wafer level packaging technology will continue to develop and innovate to meet the increasingly severe market competition and technical challenges.
