STM32 - Understanding DAC in One Text

1 DAC overview of STM32

The DAC module of STM32 is a 12 bit digital input and voltage output digital/analog converter, with two output channels, and each channel has a separate converter. In the dual DAC mode, the two channels can be converted independently, or simultaneously and synchronously update the output of the two channels. DAC can input reference voltage VREF+through pins to obtain more accurate conversion results. The DAC module is under the APB1 clock!

Note: The DAC module of STM32 only exists in high-capacity products (the FLASH capacity is between 256K and 512K).

1.1 Main characteristics

Two DAC converters: each converter corresponds to one output channel

8-bit or 12 bit monotone output

Left or right alignment of data in 12 bit mode

Synchronous update function

Noise waveform generation

Triangular wave Shape generation

Simultaneous or separate conversion of dual DAC channels

Each channel has DMA function

External trigger conversion

Input reference voltage VREF+

1.2 Block Diagram

The block diagram of a single DAC is as follows:

It is mainly divided into the following parts:

Power supply and reference voltage, output, trigger source, control register (corresponding to white) Data register DHR、 Digital to analog conversion unit.

The power supply pin has been introduced in STM32 - Understanding ADC.

There is nothing to say about the output. It should be noted that once the DAC x channel is enabled, the corresponding GPIO pin (PA4 or PA5) will be automatically connected to the analog output of the DAC

(DAC_OUTx)。 The output pins of the DAC1 and DAC2 modules are PA4 and PA5. To avoid parasitic interference and additional power consumption, when using the DAC function, the corresponding pins should be set to analog input (AIN).

The trigger sources are mainly as follows

If TENx bit is set to 1, DAC conversion can be triggered by an external event (timer counter, external interrupt line). Configure the control bit TSELx [2:0] to select one of the eight trigger events to trigger DAC conversion.

The so-called trigger refers to converting the data in the data register DORx into the signal output by the analog signal. Simply speaking, it is to refresh the output signal, because the data in the DOR data register will not be converted immediately after being updated, but will not be converted until the trigger signal.

Trigger can be selected as:

(1) The trigger mode is not used. In this mode, the DAC conversion module automatically converts once only after writing data to the DAC data register DHR.

(2) Software trigger mode: in this mode, the conversion is triggered when the command is written to the software trigger register SWTRIGR, that is, the data in the DOR register is converted.

(3) External trigger mode.

(3.1) Timer trigger, which is a periodic trigger mode, that is, periodic refresh mode. When will this method be used? Complex waveform! For example, output triangle wave. As will be mentioned later, the data generation of triangular wave is generated by a separate counter, which will add 1/minus 1 after each trigger. Imagine that if we trigger the timer to increase or decrease its output amplitude at a fixed time interval, and then set the maximum value of this counter, we can generate triangular waves of a certain frequency?

(3.2) External interrupt EXTI line trigger is mainly used for external signal control DAC conversion.

The control register mainly configures channel x, such as DMA enable, noise/triangle wave generation, trigger source selection, channel x trigger enable, etc. Details will follow.

There are 9 data registers DHR in total, but they are essentially used to store the data output from DAC. The data here will be transferred to the ODR register for DA output when appropriate.

A/D conversion unit, which loads the data in the data register into the DOR register and performs DA conversion.

The DAC output is directly controlled by the DORx register, but we cannot write data directly to the DORx register. Instead, DHRx is indirectly transferred to the DORx register to control the DAC output.

2 Function Details

2.1 DAC data format

STM32 product with dual DAC module, its DAC module has 9 data registers (DHR)! In the single channel mode, DAC1 and DAC2 are used separately, Dual channel There are also 3 registers in mode.

Three data formats in single channel mode, including 8-bit right alignment, 12 bit left alignment, and 12 bit right alignment. As shown in the figure below

The three data formats in dual channel mode are also 8-bit right aligned, 12 bit left aligned, and 13 bit right aligned. As shown in the figure below

2.2 Relationship between data registers DHR and DOR

The data register DHR is a development oriented register that can directly write data, which is the data output to the corresponding DAC channel.

The data register DOR is a register that directly controls the DAC data output. Data cannot be written to this register directly. The data of this register is transferred from the data register DHR.

If the DAC is not output by enabling external trigger, the data stored in the register DHR will be automatically transferred to the DOR after an APB1 clock cycle.

If the external departure mode is enabled, it shall be transmitted to DOR three APB1 clock cycles after the external trigger signal occurs. As shown in the figure below

2.3 DAC output voltage

Range: 0~Vref

Relationship: DAC output=Vref x (DOR/4095)

DAC has an output buffer function, which can increase the output drive capability of the IO port, but there is a problem that the output cannot return to zero! This function is not recommended.

2.4 Noise generation

Operation.. It's OK to generate noise!

STM32 uses linear feedback to generate noise for the register (LFSR), as shown in the following figure. To understand the principle of noise generated by such registers, here and here. Don't go deep into its principle first, just know it can!

Set WAVEx [1:0] bit of DAC_CR register to '01' to select DAC noise generation function, and update the value of this register after 3 APB1 clock cycles after each trigger event. Set the MAMPx [3:0] bit of the DAC_CR register to mask the data of some or all LFSR registers.

Whether generating noise or triangular wave, the final output data of DAC is the addition of LSFR value and DAC_DHRx value, and then the overflow bit is removed. It is then written to the DAC_DORx register. (The following figure about triangular wave can be explained vividly)

In this way, if overflow occurs, some DC parts can be removed (that is, the value part in DAC_DHRx).

What is removing overflow bits?

For example, for an 8-bit data, the maximum number of bits that can be represented is 0xFF, and then add 1 to become 0x00, which is called removing the overflow bit. Because 0xFF+0x01=0x100, the highest bit here is the overflow bit for 8-bit data, which becomes 0x00 after removal.

Note: In order to generate noise or triangular wave, DAC triggering must be enabled (set TENx bit of CR register as 1). This is because the DOR register can be modified (modified by the noise algorithm circuit or the triangle wave counter) without modifying the value of the DHR register for output noise or triangle wave, and the modification is periodic. Therefore, the DA output must be constantly updated by triggering. Generally, the timer triggering method is used.

2.5 Triangular wave generation

Triangle wave can be added on the basis of DC signal output by DACx. Set WAVEx [1:0] bit to '10' to select the triangle wave generation function of DAC. Set the MAMPx [3:0] bit of the DAC_CR register to select the amplitude of the triangular wave.

There is a triangle wave counter inside the DACx module, which accumulates 1 after 3 APB1 clock cycles after each trigger event. The counter value is added to the value of the DAC_DORx register, and the overflow bit is discarded and written to the DAC_DORx register. When the value passed into the DAC_DORx register is less than the maximum amplitude defined by the MAMP [3:0] bit, the triangle wave counter will accumulate gradually. Once the set maximum amplitude is reached, the counter starts to decrease, and then starts to accumulate after reaching 0.

Note: The MAMP [3:0] bit must be set before enabling DAC, otherwise its value cannot be modified.

2.6 Dual DAC channels

DAC supports the simultaneous use of two modules and has a special data register in dual channel mode (mentioned above).

There are 11 modes available in dual channel mode.

2.6.1 Independent trigger without waveform generator

When the DAC channel 1 trigger event occurs, the value of register DHR1 (after delaying 3 APB1 clock cycles) is transferred to register DAC_DOR1.

When the DAC channel 2 trigger event occurs, the value of register DHR2 (after delaying 3 APB1 clock cycles) is transferred to register DAC_DOR2.

2.6.2 Independent Trigger Using the Same LFSR

When the DAC channel 1 trigger event occurs, the LFSR1 counter value with the same mask is added to the DHR1 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR1, and then the LFSR1 counter is updated.

When the DAC channel 2 trigger event occurs, the LFSR2 counter value with the same mask is added to the DHR2 register value, and the result (after delaying 3 APB1 clock cycles) is passed into the register DAC_DOR2, and then the LFSR2 counter is updated.

2.6.3 Independent triggering using different LFSRs

When the DAC channel 1 trigger event occurs, the LFSR1 counter value masked according to the MAMP1 [3:0] is added to the DHR1 register value, (after delaying 3 APB1 clock cycles) the result is transferred to the register DAC_DOR1, and then the LFSR1 counter is updated.

When the DAC channel 2 trigger event occurs, the LFSR2 counter value masked according to the MAMP2 [3:0] is added to the DHR2 register value, (after delaying 3 APB1 clock cycles) the result is transferred to the register DAC_DOR2, and then the LFSR2 counter is updated.

2.6.4 Independent trigger for generating the same triangle wave

When the DAC channel 1 trigger event occurs, the same triangle amplitude value plus the value of the DHR1 register (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR1, and then the DAC channel 1 triangle wave counter is updated.

When the DAC channel 2 trigger event occurs, the same triangle amplitude value plus the value of the DHR2 register (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR2, and then the DAC channel 2 triangle counter is updated.

2.6.5 Independent triggering for generating different triangular waves

When the DAC channel 1 trigger event occurs, the triangle wave amplitude value set by MAMP1 [3:0] plus the DHR1 register value (after delaying 3 APB1 clock cycles) is transferred to the register DAC_DOR1, and then the DAC channel 1 triangle wave counter is updated.

When the DAC channel 2 trigger event occurs, the triangle wave amplitude value set by MAMP2 [3:0] plus the DHR2 register value (after delaying 3 APB1 clock cycles) is transferred to the register DAC_DOR2, and then the DAC channel 2 triangle wave counter is updated.

2.6.6 Simultaneous software startup

In this configuration, after an APB1 clock cycle, the values of DHR1 and DHR2 registers are transferred to DAC_DOR1 and DAC_DOR2 registers respectively.

2.6.7 Simultaneous triggering without waveform generator

When a trigger event occurs (after delaying 3 APB1 clock cycles), the values of DHR1 and DHR2 registers are transferred to DAC_DOR1 and DAC_DOR2 registers respectively.

2.6.8 Simultaneous triggering using the same LFSR

When a trigger event occurs, the LFSR1 counter value masked by MAMP1 [3:0] is added to the value of the DHR1 register, and the result (after three APB1 clock cycles are delayed) is transferred to the DAC_DOR1 register, and then the LFSR1 counter is updated.

Similarly, the LFSR2 counter value of the mask set by MAMP1 [3:0] is added to the value of the DHR2 register, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR2, and then the LFSR2 counter is updated.

2.6.9 Simultaneous triggering using different LFSRs

When a trigger event occurs, the LFSR1 counter value with the same mask is added to the DHR1 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR1, and then the LFSR1 counter is updated.

At the same time, the LFSR2 counter value with the same mask is added to the DHR2 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR2, and then the LFSR2 counter is updated.

2.6.10 Simultaneous triggering using the same triangle wave generator

When a trigger event occurs, the same triangle amplitude value is added to the DHR1 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR1, and then the LFSR1 counter is updated.

At the same time, the same triangle amplitude value is added to the DHR2 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR2, and then the LFSR2 counter is updated.

2.6.11 Simultaneous triggering with different triangle wave generators

When a trigger event occurs, the triangle amplitude value set by MAMP1 [3:0] is added to the value of the DHR1 register, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR1, and then the LFSR1 counter is updated.

At the same time, the triangle amplitude value set by MAMP2 [3:0] is added to the DHR2 register value, and the result (after three APB1 clock cycles are delayed) is transferred to the register DAC_DOR2, and then the LFSR2 counter is updated.

3 Related registers

3.1 DAC control register (DAC_CR)

This register is used to configure DAC1 (low 8 bits) and DAC2 (high 8 bits), here only DAC1 is mentioned.

3.2 DAC software trigger register (DAC_SWTRIGR)

Control software triggering of DAC1 and DAC2.

The other controls DAC2.

3.3 Various DHR data registers

The register format is shown in the picture in section 2.1. A total of 9.

3.4 Two DOR data registers

The register that ultimately controls the DAC output.

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