This book first proposes seven evaluation indicators of an instruction set, including cost, simplicity, performance, separation of architecture and implementation, space for improvement, code size, and ease of programming/compiling/linking. It also introduces the delicate design and numerous trade-offs of RISC-V from a system wide perspective around these seven evaluation indicators. At the same time, the book also introduces the design of x86, ARM and MIPS, and compares them quantitatively through insert sorting and DAXPY (double precision multiply add) programs, highlighting the advantages of RISC-V, and deeply explaining the impact of instruction set design on computer systems. If you are a student, this book will be an excellent extracurricular reading material, which will help you establish a complete concept of computer system; If you are a teacher, this book will provide you with a wealth of real cases, which can bring new inspiration to your teaching work; If you are a practitioner in a related field, this book is not only a broadening of your vision, but also a convenient reference manual to help you complete your work more easily.
The Design of RISC-V Open Architecture was written by David Patterson, the author of RISC-V architecture and a famous computer architecture expert. It clearly and thoroughly outlines the whole picture of RISC-V architecture with the most concise pen and ink. The book creatively organizes the content according to the modular instructions of RISC-V to help readers deeply understand the key characteristics of RISC-V, This book is worth intensive reading for every reader interested in RISC-V, and can be used as a desk reference book for practitioners at any time.
In addition, this book also introduces the design of x86, ARM and MIPS, and highlights the advantages of RISC-V through comparative analysis.
The Design of RISC-V Open Architecture was translated by Bao Yungang, a teacher from the Institute of Computing, CAS.
| catalog ：
Chapter 1 Why RISC-V 1
1.1 Introduction 2
1.2 Modular ISA and Incremental ISA 3
1.3 Introduction to ISA Design 5
1.4 Overview of the whole book 11
1.5 Conclusion 13
1.6 Extended Reading 14
Chapter 2 RV32I: RISC-V Basic Integer Instruction Set 16
2.1 Introduction 17
2.2 RV32I command format 18
2.3 RV32I register 21
2.4 RV32I integer calculation 23
2.5 RV32I data retrieval and storage 25
2.6 RV32I conditional branching 26
2.7 Unconditional jump of RV32I 27
2.8 Other RV32I Directives 28
2.9 Comparison of RV32I, ARM-32, MIPS-32 and x86-32 by insertion sorting 28
2.10 Conclusion 34
2.11 Extended Reading 36
Chapter 3 RISC-V Assembly Language37
3.1 Introduction 38
3.2 Calling Conventions 38
3.3 Assembler 41
3.4 Linker 46
3.5 Static link and dynamic link 49
3.6 Loader 49
3.7 Conclusion 50
3.8 Extended Reading 50
Chapter 4 RV32M: Multiplication and Division Instructions 51
4.1 Introduction 52
4.2 Conclusion 54
4.3 Extended Reading 55
Chapter 5 RV32F and RV32D: Single and Double Precision Floating Point Numbers 56
5.1 Introduction 57
5.2 Floating point registers60
5.3 Floating point access, storage and arithmetic operations62
5.4 Floating point conversion and data transfer63
5.5 Other floating point instructions 63
5.6 Compare RV32FD, ARM-32, MIPS-32 and x86-32 65 through DAXPY program
5.7 Conclusion 68
5.8 Extended Reading 68
Chapter 6 RV32A: Atomic Directive 70
6.1 Introduction 71
6.2 Conclusion 73
6.3 Extended Reading 74
Chapter 7 RV32C: Compression Instruction 75
7.1 Introduction 76
7.2 Compare RV32GC, Thumb-2, microMIPS and x86-32 81
7.3 Conclusion 82
7.4 Extended Reading 82
Chapter 8 RV32V: Vector 83
8.1 Introduction 84
8.2 Vector calculation instruction 85
8.3 Vector registers and dynamic types86
8.4 Vector access and storage 88
8.5 Parallelism of vector operation89
8.6 Conditional execution of vector operation90
8.7 Other vector instructions90
8.8 Example: writing DAXPY program with RV32V 92
8.9 Comparison of RV32V, MIPS-32 MSA SIMD and x86-32 AVX SIMD · 93
8.10 Conclusion 97
8.11 Extended reading99
Chapter 9 RV64: 64 bit address instruction · 100
9.1 Introduction 101
9.2 Comparing RV64 with other 64 bit ISA 105 by insertion sorting
9.3 Program size 112
9.4 Conclusion 113
9.5 Extended reading 114
Chapter 10 RV32/64 Privilege Architecture 115
10.1 Introduction 116
10.2 Machine mode of simple embedded system117
10.3 Exception handling of machine mode119
10.4 User mode and process isolation in embedded system124
10.5 Supervision mode of modern operating system126
10.6 Page Virtual Memory128
10.7 Identification and performance CSR 133
10.8 Conclusion 136
10.9 Extended Reading 136
Chapter 11 Optional Extension of RISC-V in the Future 137
11.1 "B" standard extension: bit operation 138
11.2 "E" standard extension: embedded 138
11.3 "H" privileged state architecture extension: support the hypervisor 138
11.4 "J" standard extension: dynamic translation language · 138
11.5 "L" standard extension: decimal floating point 139
11.6 "N" standard extension: user mode interrupt 139
11.7 "P" standard extension: compact SIMD instruction 139
11.8 "Q" standard extension: four precision floating point 140
11.9 Conclusion 140
Appendix A List of RISC-V Directives 141
Appendix B Literal translation of RISC-V to other ISA 187
Index 195
| About the author:
David Patterson has been a professor of computer science at the University of California, Berkeley for 40 years. He retired in 2016 and joined the "Google Brain" project as an outstanding engineer. He also served as the Vice Chairman of the Board of Directors of RISC-V International Foundation and the Director of RISC-V International Open Source Laboratory.
He was appointed chairman of Berkeley Computer Science Department, and was elected chairman of CRA (Computing Research Association) and ACM (Association for Computing Machinery).
In the 1980s, he led the project of four generations of Reduced Instruction Set Computer (RISC), so Berkeley's new RISC was named "RISC Five" (the fifth generation RISC). He and Andrew Waterman are one of the four RISC-V architects.
In addition to RISC, his famous research project is Redundant Array of Cheap Disks (RAID, Redundant Arrays of Inexpensive Disks）。 Based on this research, he has published many papers, published 7 books, and won more than 40 honors, including being elected as an academician of the National Academy of Engineering and the National Academy of Sciences of the United States, being elected to the "Silicon Valley Engineering Hall of Fame", and being awarded the Outstanding Achievement Award by ACM, CRA and SIGARCH. His teaching awards include the Outstanding Teaching Award (University of California, Berkeley), the Karlstrom Outstanding Educator Award (ACM), the Mulligan Education Medal (IEEE), and the Text and Academic Authors Association twice.
His recent honors include Tapia Achievement Award, BBVA Foundation Knowledge Frontier Award and ACM Turing Award, the latter two of which were jointly awarded with John Hennessy. He received all his degrees from the University of California, Los Angeles, and was awarded the Outstanding Engineering Alumni Award by the University. He grew up in Southern California. His hobbies are body surfing, cycling and football with his sons, and hiking with his wife. They fell in love in high school and celebrated their 55th wedding anniversary in 2022.
Andrew Waterman is the chief engineer and co-founder of SiFive. SiFive was founded by the inventors of RISC-V architecture to provide low-cost customized chips based on RISC-V. He received a doctorate in computer science from the University of California, Berkeley. In the meantime, he was tired of the unpredictable changes of the existing instruction set architecture, so he participated in the design of RISC-V ISA and the first RISC-V microprocessor. Andrew has made major contributions to many open source projects, including the open source Rocket chip generator based on RISC-V instruction set, Chisel hardware construction language, and the RISC-V version migration of Linux operating system kernel, GNU C compiler and C library. He also received a master's degree from the University of California, Berkeley, during which he carried out the preliminary work of RISC-V compression and expansion. He also received a Bachelor of Engineering degree from Duke University.
