Thanks for the clue delivery of netizen Daniel Wu of South China! Recently, relevant information about the execution engine of AMD Zen 5 processor was shared. It is understood that Zen 5 will use a real 512 bit floating point unit (FPU). This upgrade will have higher performance in processing 512 bit AVX or VNNI instructions.
It is also learned from the report that AMD has upgraded relevant components for 512 bit FPUs, including improving the capacity of L1 DTLB and expanding the load store queue. In addition, the bandwidth of L1 data cache has doubled, and the size has also increased by 50%. The L1D size has increased from 32KB in "Zen 4" to 48KB now.
In addition to FPU, AMD also increased the number of integer execution pipes from 8 (Zen 4) to 10. The exclusive L2 cache size of each kernel is still 1MB. In general, these upgrades will further improve the performance of the Zen 5 processor in multithreaded applications.
In addition, it should be noted that the dual 256 bit FPU is used when executing AVX-512 instruction workload, and the real 512 bit FPU will be used in Zen 5 for support This improvement will make AMD processors more efficient and powerful in the future.
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Thanks for the clue delivery of netizen Daniel Wu of South China! Recently, relevant information about the execution engine of AMD Zen 5 processor was shared. It is understood that Zen 5 will use a real 512 bit floating point unit (FPU). This upgrade will have higher performance in processing 512 bit AVX or VNNI instructions. It is also learned from the report that AMD is 512 bit FPU
