There may be a method error. Please refer to the following method.
The method of outputting analog waveform is as follows: 1. Open the Quartus II software, 2. Select File → New Project Wizard to create a new project. 3. Click Next to enter. (Any design is a project. You must first create a folder for this project to place all the files related to this project, such as E/eda in English.) Then three items will appear, E/eda, COUNT, COUNT. Click Next to enter the next item. If the first name is left blank, click Next to enter the dialog box.In this dialog box, specify the target device (we select the EP1C6240C8 of the Cyclone series used on the QuickEDA core board.) Next to finish 4. Select File → New - VHDL file to copy your programming 5. File → save as (create a new folder in English) The file name must be changed to COUNT (keep consistent with the entity, and the default file name is VHDL1) 6. In the Quartus II main interface, select Processing → Start Compilation to compile the whole process, and "successful" will be displayed 7. In the Quartus II main interface, select File → New to open the new file dialog box, where you can select Vector Waveform File; 8. Double click the left mouse button in the Nane column to pop up the dialog box. 9. Click the Node Finder button 5, select Pins: all in the Filter column, click the List button, and a dialog box as shown in the figure pops up. 10. Click the button and press OK twice. 11. Set the simulation end time. Select Edit → End time... in the Quartus II main interface to open the dialog box, and set the simulation end time to 20us. 12. Edit input node waveform 1) Select clk, click Overwrite Clock in the toolbar, open the dialog box shown in the figure, and set the CLK cycle to 50ns. 2) Set clr to "0" (there is a 0 rectangular wave vertically on the left side of the oscillogram).(You can click the zoom in/out button and press the right button when zooming out) 13. Save the simulation waveform file, File → save, just save by default 14. Functional simulation. 1) In the Quartus II main interface, select Processing → Simulate Tool, 2) Select Functional under Simulation mode, and click Generate Functional Simulation Netlist.Click the Start button to start the simulation.,After the simulation, click the Report button to open the simulation result window (the waveform will come out), in which the design results can be observed. The delay time of the device is not considered in the function simulation.
First, quartus's simulation is divided into sequential simulation and functional simulation Set input in oscillogram It's better to give a picture to see where the problem is
